s390: Use risbgz for AND

        * config/s390/s390.md (*anddi3_cc): Add risbg alternative.
        (*anddi3_cconly, *anddi3): Likewise.
        (*andsi3, *andsi3_cconly, *andsi3_zarch): Likewise.

Co-Authored-By: Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

From-SVN: r194642

2 files changed, 66 insertions, 45 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e0fa728..7972aa1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -12,6 +12,10 @@
 
 	* config/s390/s390.md (*insv_l_di_reg_extimm): Un-macroize from :P.
 
+	* config/s390/s390.md (*anddi3_cc): Add risbg alternative.
+	(*anddi3_cconly, *anddi3): Likewise.
+	(*andsi3, *andsi3_cconly, *andsi3_zarch): Likewise.
+
 2012-12-20  Thomas Schwinge  <thomas@codesourcery.com>
 
 	PR bootstrap/55202
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 48133ea..0887eae 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -5999,44 +5999,50 @@
 
 (define_insn "*anddi3_cc"
   [(set (reg CC_REGNUM)
-        (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
-                         (match_operand:DI 2 "general_operand"      " d,d,RT"))
-                 (const_int 0)))
-   (set (match_operand:DI 0 "register_operand"                      "=d,d, d")
+        (compare
+	  (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
+                  (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
+          (const_int 0)))
+   (set (match_operand:DI 0 "register_operand"               "=d,d, d,    d")
         (and:DI (match_dup 1) (match_dup 2)))]
-  "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
+  "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
   "@
    ngr\t%0,%2
    ngrk\t%0,%1,%2
-   ng\t%0,%2"
-  [(set_attr "op_type"  "RRE,RRF,RXY")
-   (set_attr "cpu_facility" "*,z196,*")
-   (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
+   ng\t%0,%2
+   risbg\t%0,%1,%s2,128+%e2,0"
+  [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
+   (set_attr "cpu_facility" "*,z196,*,z10")
+   (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
 
 (define_insn "*anddi3_cconly"
   [(set (reg CC_REGNUM)
-        (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
-                         (match_operand:DI 2 "general_operand"      " d,d,RT"))
+        (compare
+	  (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0,    d")
+                  (match_operand:DI 2 "general_operand"      " d,d,RT,NxxDq"))
                  (const_int 0)))
-   (clobber (match_scratch:DI 0                                     "=d,d, d"))]
-  "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
+   (clobber (match_scratch:DI 0                              "=d,d, d,    d"))]
+  "TARGET_ZARCH
+   && s390_match_ccmode(insn, CCTmode)
    /* Do not steal TM patterns.  */
    && s390_single_part (operands[2], DImode, HImode, 0) < 0"
   "@
    ngr\t%0,%2
    ngrk\t%0,%1,%2
-   ng\t%0,%2"
-  [(set_attr "op_type"  "RRE,RRF,RXY")
-   (set_attr "cpu_facility" "*,z196,*")
-   (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
+   ng\t%0,%2
+   risbg\t%0,%1,%s2,128+%e2,0"
+  [(set_attr "op_type"  "RRE,RRF,RXY,RIE")
+   (set_attr "cpu_facility" "*,z196,*,z10")
+   (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
 
 (define_insn "*anddi3"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-                            "=d,d,    d,    d,    d,    d,    d,    d,d,d, d,   AQ,Q")
-        (and:DI (match_operand:DI 1 "nonimmediate_operand"
-                            "%d,o,    0,    0,    0,    0,    0,    0,0,d, 0,    0,0")
-                (match_operand:DI 2 "general_operand"
-                            "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q")))
+            "=d,d,    d,    d,    d,    d,    d,    d,d,d, d,    d,   AQ,Q")
+        (and:DI
+	  (match_operand:DI 1 "nonimmediate_operand"
+            "%d,o,    0,    0,    0,    0,    0,    0,0,d, 0,    d,    0,0")
+          (match_operand:DI 2 "general_operand"
+            "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
   "@
@@ -6051,10 +6057,11 @@
    ngr\t%0,%2
    ngrk\t%0,%1,%2
    ng\t%0,%2
+   risbg\t%0,%1,%s2,128+%e2,0
    #
    #"
-  [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
-   (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*")
+  [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
+   (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
    (set_attr "z10prop" "*,
                         *,
                         z10_super_E1,
@@ -6066,6 +6073,7 @@
                         z10_super_E1,
                         *,
                         z10_super_E1,
+                        z10_super_E1,
                         *,
                         *")])
 
@@ -6086,10 +6094,12 @@
 
 (define_insn "*andsi3_cc"
   [(set (reg CC_REGNUM)
-        (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
-                         (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
-                 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand"                      "=d,d,d,d,d")
+        (compare
+	  (and:SI
+	    (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
+            (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
+          (const_int 0)))
+   (set (match_operand:SI 0 "register_operand"         "=d,d,d,d,d,    d")
         (and:SI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
@@ -6097,17 +6107,21 @@
    nr\t%0,%2
    nrk\t%0,%1,%2
    n\t%0,%2
-   ny\t%0,%2"
-  [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
-   (set_attr "cpu_facility" "*,*,z196,*,*")
-   (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
+   ny\t%0,%2
+   risbg\t%0,%1,%t2,128+%f2,0"
+  [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
+   (set_attr "cpu_facility" "*,*,z196,*,*,z10")
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
+			z10_super_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*andsi3_cconly"
   [(set (reg CC_REGNUM)
-        (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
-                         (match_operand:SI 2 "general_operand"      "Os,d,d,R,T"))
-                 (const_int 0)))
-   (clobber (match_scratch:SI 0                                     "=d,d,d,d,d"))]
+        (compare
+	  (and:SI
+	    (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0,    d")
+            (match_operand:SI 2 "general_operand"      "Os,d,d,R,T,NxxSq"))
+          (const_int 0)))
+   (clobber (match_scratch:SI 0                        "=d,d,d,d,d,    d"))]
   "s390_match_ccmode(insn, CCTmode)
    /* Do not steal TM patterns.  */
    && s390_single_part (operands[2], SImode, HImode, 0) < 0"
@@ -6116,19 +6130,20 @@
    nr\t%0,%2
    nrk\t%0,%1,%2
    n\t%0,%2
-   ny\t%0,%2"
-  [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY")
-   (set_attr "cpu_facility" "*,*,z196,*,*")
+   ny\t%0,%2
+   risbg\t%0,%1,%t2,128+%f2,0"
+  [(set_attr "op_type"  "RIL,RR,RRF,RX,RXY,RIE")
+   (set_attr "cpu_facility" "*,*,z196,*,*,z10")
    (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
-                        z10_super_E1,z10_super_E1")])
+                        z10_super_E1,z10_super_E1,z10_super_E1")])
 
 (define_insn "*andsi3_zarch"
   [(set (match_operand:SI 0 "nonimmediate_operand"
-                            "=d,d,    d,    d, d,d,d,d,d,   AQ,Q")
+                            "=d,d,    d,    d, d,d,d,d,d,    d,   AQ,Q")
         (and:SI (match_operand:SI 1 "nonimmediate_operand"
-			    "%d,o,    0,    0, 0,0,d,0,0,    0,0")
+			    "%d,o,    0,    0, 0,0,d,0,0,    d,    0,0")
                 (match_operand:SI 2 "general_operand"
-			    " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q")))
+			    " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
   "@
@@ -6141,10 +6156,11 @@
    nrk\t%0,%1,%2
    n\t%0,%2
    ny\t%0,%2
+   risbg\t%0,%1,%t2,128+%f2,0
    #
    #"
-  [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
-   (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*")
+  [(set_attr "op_type"  "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
+   (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
    (set_attr "z10prop" "*,
                         *,
                         z10_super_E1,
@@ -6154,6 +6170,7 @@
                         *,
                         z10_super_E1,
                         z10_super_E1,
+                        z10_super_E1,
                         *,
                         *")])