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| author | Mary Bennett <mary.bennett@embecosm.com> | 2023-12-15 16:10:15 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-12-15 16:10:15 -0700 |
| commit | e0fe3ab96848633e1e09f20ddbf32bdb6552db11 (patch) | |
| tree | 266cae2eb7a979271228646fd7dca71bd28b231b | |
| parent | 14876d6aa73b9e9385313c857ab6f399e4823bf8 (diff) | |
| download | gcc-e0fe3ab96848633e1e09f20ddbf32bdb6552db11.zip gcc-e0fe3ab96848633e1e09f20ddbf32bdb6552db11.tar.gz gcc-e0fe3ab96848633e1e09f20ddbf32bdb6552db11.tar.bz2 | |
[PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors
gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
| -rw-r--r-- | gcc/config/riscv/constraints.md | 15 | ||||
| -rw-r--r-- | gcc/config/riscv/corev.md | 4 |
2 files changed, 10 insertions, 9 deletions
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index d0f95b2..de4359a 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -143,13 +143,6 @@ (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS" "An integer register for ZFA or XTheadFmv.") -;; CORE-V Constraints -(define_constraint "CVP2" - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2" - (and (match_code "const_int") - (and (match_test "IN_RANGE (ival, 0, 1073741823)") - (match_test "exact_log2 (ival + 1) != -1")))) - ;; Vector constraints. (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" @@ -261,3 +254,11 @@ A MEM with a valid address for th.[l|s]*ur* instructions." (and (match_code "mem") (match_test "th_memidx_legitimate_index_p (op, true)"))) + +;; CORE-V Constraints +(define_constraint "CV_alu_pow2" + "@internal + Checking for CORE-V ALU clip if ival plus 1 is a power of 2" + (and (match_code "const_int") + (and (match_test "IN_RANGE (ival, 0, 1073741823)") + (match_test "exact_log2 (ival + 1) != -1")))) diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index c7a2ba0..92bf0b5 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -516,7 +516,7 @@ (define_insn "riscv_cv_alu_clip" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIP))] "TARGET_XCVALU && !TARGET_64BIT" @@ -529,7 +529,7 @@ (define_insn "riscv_cv_alu_clipu" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIPU))] "TARGET_XCVALU && !TARGET_64BIT" |