[AArch64] Add support for SVE CNOT

This patch adds support for predicated and unpredicated CNOT
(logical NOT on integers).  In RTL terms, this is a select between
1 and 0 in which the predicate is fed by a comparison with zero.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/predicates.md (aarch64_simd_imm_one): New predicate.
	* config/aarch64/aarch64-sve.md (*cnot<mode>): New pattern.
	(*cond_cnot<mode>_2, *cond_cnot<mode>_any): Likewise.

gcc/testsuite/
	* gcc.target/aarch64/sve/cnot_1.c: New test.
	* gcc.target/aarch64/sve/cond_cnot_1.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_1_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_2.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_2_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_3.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_3_run.c: Likewise.

From-SVN: r274438

11 files changed, 341 insertions, 0 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b5b4414..701f75c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,11 @@
 2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
 
+	* config/aarch64/predicates.md (aarch64_simd_imm_one): New predicate.
+	* config/aarch64/aarch64-sve.md (*cnot<mode>): New pattern.
+	(*cond_cnot<mode>_2, *cond_cnot<mode>_any): Likewise.
+
+2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+
 	* config/aarch64/iterators.md (SVE_INT_UNARY): Add clrsb and clz.
 	(optab, sve_int_op): Handle them.
 	* config/aarch64/aarch64-sve.md: Expand comment.
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 7e696d8..e3654aa 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -54,6 +54,7 @@
 ;;
 ;; == Unary arithmetic
 ;; ---- [INT] General unary arithmetic corresponding to rtx codes
+;; ---- [INT] Logical inverse
 ;; ---- [FP] General unary arithmetic corresponding to unspecs
 ;; ---- [PRED] Inverse
 
@@ -1455,6 +1456,95 @@
 )
 
 ;; -------------------------------------------------------------------------
+;; ---- [INT] Logical inverse
+;; -------------------------------------------------------------------------
+
+;; Predicated logical inverse.
+(define_insn "*cnot<mode>"
+  [(set (match_operand:SVE_I 0 "register_operand" "=w")
+	(unspec:SVE_I
+	  [(unspec:<VPRED>
+	     [(match_operand:<VPRED> 1 "register_operand" "Upl")
+	      (match_operand:SI 5 "aarch64_sve_ptrue_flag")
+	      (eq:<VPRED>
+		(match_operand:SVE_I 2 "register_operand" "w")
+		(match_operand:SVE_I 3 "aarch64_simd_imm_zero"))]
+	     UNSPEC_PRED_Z)
+	   (match_operand:SVE_I 4 "aarch64_simd_imm_one")
+	   (match_dup 3)]
+	  UNSPEC_SEL))]
+  "TARGET_SVE"
+  "cnot\t%0.<Vetype>, %1/m, %2.<Vetype>"
+)
+
+;; Predicated logical inverse, merging with the first input.
+(define_insn_and_rewrite "*cond_cnot<mode>_2"
+  [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
+	(unspec:SVE_I
+	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
+	   ;; Logical inverse of operand 2 (as above).
+	   (unspec:SVE_I
+	     [(unspec:<VPRED>
+		[(match_operand 5)
+		 (const_int SVE_KNOWN_PTRUE)
+		 (eq:<VPRED>
+		   (match_operand:SVE_I 2 "register_operand" "0, w")
+		   (match_operand:SVE_I 3 "aarch64_simd_imm_zero"))]
+		UNSPEC_PRED_Z)
+	      (match_operand:SVE_I 4 "aarch64_simd_imm_one")
+	      (match_dup 3)]
+	     UNSPEC_SEL)
+	   (match_dup 2)]
+	  UNSPEC_SEL))]
+  "TARGET_SVE"
+  "@
+   cnot\t%0.<Vetype>, %1/m, %0.<Vetype>
+   movprfx\t%0, %2\;cnot\t%0.<Vetype>, %1/m, %2.<Vetype>"
+  "&& !CONSTANT_P (operands[5])"
+  {
+    operands[5] = CONSTM1_RTX (<VPRED>mode);
+  }
+  [(set_attr "movprfx" "*,yes")]
+)
+
+;; Predicated logical inverse, merging with an independent value.
+;;
+;; The earlyclobber isn't needed for the first alternative, but omitting
+;; it would only help the case in which operands 2 and 6 are the same,
+;; which is handled above rather than here.  Marking all the alternatives
+;; as earlyclobber helps to make the instruction more regular to the
+;; register allocator.
+(define_insn_and_rewrite "*cond_cnot<mode>_any"
+  [(set (match_operand:SVE_I 0 "register_operand" "=&w, ?&w, ?&w")
+	(unspec:SVE_I
+	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
+	   ;; Logical inverse of operand 2 (as above).
+	   (unspec:SVE_I
+	     [(unspec:<VPRED>
+		[(match_operand 5)
+		 (const_int SVE_KNOWN_PTRUE)
+		 (eq:<VPRED>
+		   (match_operand:SVE_I 2 "register_operand" "w, w, w")
+		   (match_operand:SVE_I 3 "aarch64_simd_imm_zero"))]
+		UNSPEC_PRED_Z)
+	      (match_operand:SVE_I 4 "aarch64_simd_imm_one")
+	      (match_dup 3)]
+	     UNSPEC_SEL)
+	   (match_operand:SVE_I 6 "aarch64_simd_reg_or_zero" "0, Dz, w")]
+	  UNSPEC_SEL))]
+  "TARGET_SVE && !rtx_equal_p (operands[2], operands[6])"
+  "@
+   cnot\t%0.<Vetype>, %1/m, %2.<Vetype>
+   movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;cnot\t%0.<Vetype>, %1/m, %2.<Vetype>
+   movprfx\t%0, %6\;cnot\t%0.<Vetype>, %1/m, %2.<Vetype>"
+  "&& !CONSTANT_P (operands[5])"
+  {
+    operands[5] = CONSTM1_RTX (<VPRED>mode);
+  }
+  [(set_attr "movprfx" "*,yes,yes")]
+)
+
+;; -------------------------------------------------------------------------
 ;; ---- [FP] General unary arithmetic corresponding to unspecs
 ;; -------------------------------------------------------------------------
 ;; Includes:
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 466d56d..5c85671 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -460,6 +460,10 @@
   (and (match_code "const,const_vector")
        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 
+(define_predicate "aarch64_simd_imm_one"
+  (and (match_code "const_vector")
+       (match_test "op == CONST1_RTX (GET_MODE (op))")))
+
 (define_predicate "aarch64_simd_or_scalar_imm_zero"
   (and (match_code "const_int,const_double,const,const_vector")
        (match_test "op == CONST0_RTX (GET_MODE (op))")))
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 1a2d800..167cbfc 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,15 @@
 2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
 
+	* gcc.target/aarch64/sve/cnot_1.c: New test.
+	* gcc.target/aarch64/sve/cond_cnot_1.c: Likewise.
+	* gcc.target/aarch64/sve/cond_cnot_1_run.c: Likewise.
+	* gcc.target/aarch64/sve/cond_cnot_2.c: Likewise.
+	* gcc.target/aarch64/sve/cond_cnot_2_run.c: Likewise.
+	* gcc.target/aarch64/sve/cond_cnot_3.c: Likewise.
+	* gcc.target/aarch64/sve/cond_cnot_3_run.c: Likewise.
+
+2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
+
 	* gcc.target/aarch64/vect-clz.c: Force SVE off.
 	* gcc.target/aarch64/sve/clrsb_1.c: New test.
 	* gcc.target/aarch64/sve/clrsb_1_run.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cnot_1.c b/gcc/testsuite/gcc.target/aarch64/sve/cnot_1.c
new file mode 100644
index 0000000..5fa3346
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cnot_1.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+
+#include <stdint.h>
+
+#define DEF_LOOP(TYPE)						\
+  void __attribute__ ((noipa))					\
+  test_##TYPE (TYPE *restrict r, TYPE *restrict a, int n)	\
+  {								\
+    for (int i = 0; i < n; ++i)					\
+      r[i] = !a[i];						\
+  }
+
+#define TEST_ALL(T)		\
+  T (int8_t)			\
+  T (int16_t)			\
+  T (int32_t)			\
+  T (int64_t)			\
+  T (uint8_t)			\
+  T (uint16_t)			\
+  T (uint32_t)			\
+  T (uint64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-not {\tsel\t} } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_1.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_1.c
new file mode 100644
index 0000000..bd87766
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+
+#include <stdint.h>
+
+#define DEF_LOOP(TYPE)					\
+  void __attribute__ ((noipa))				\
+  test_##TYPE (TYPE *__restrict r, TYPE *__restrict a,	\
+	       TYPE *__restrict b, int n)		\
+  {							\
+    for (int i = 0; i < n; ++i)				\
+      r[i] = a[i] == 0 ? !b[i] : b[i];			\
+  }
+
+#define TEST_ALL(T) \
+  T (int8_t) \
+  T (uint8_t) \
+  T (int16_t) \
+  T (uint16_t) \
+  T (int32_t) \
+  T (uint32_t) \
+  T (int64_t) \
+  T (uint64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
+
+/* { dg-final { scan-assembler-not {\tmov\tz} } } */
+/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
+/* Currently we canonicalize the ?: so that !b[i] is the "false" value.  */
+/* { dg-final { scan-assembler-not {\tsel\t} { xfail *-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_1_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_1_run.c
new file mode 100644
index 0000000..802bcbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_1_run.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target aarch64_sve_hw } } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+
+#include "cond_cnot_1.c"
+
+#define N 99
+
+#define TEST_LOOP(TYPE)						\
+  {								\
+    TYPE r[N], a[N], b[N];					\
+    for (int i = 0; i < N; ++i)					\
+      {								\
+	a[i] = (i % 3) < (i % 5);				\
+	b[i] = i % 7 < 3;					\
+	asm volatile ("" ::: "memory");				\
+      }								\
+    test_##TYPE (r, a, b, N);					\
+    for (int i = 0; i < N; ++i)					\
+      {								\
+	TYPE expected = a[i] == 0 ? !b[i] : b[i];		\
+	if (r[i] != expected)					\
+	  __builtin_abort ();					\
+	asm volatile ("" ::: "memory");				\
+      }								\
+  }
+
+int
+main (void)
+{
+  TEST_ALL (TEST_LOOP)
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_2.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_2.c
new file mode 100644
index 0000000..d689e21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_2.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+
+#include <stdint.h>
+
+#define DEF_LOOP(TYPE)					\
+  void __attribute__ ((noipa))				\
+  test_##TYPE (TYPE *__restrict r, TYPE *__restrict a,	\
+	       TYPE *__restrict b, int n)		\
+  {							\
+    for (int i = 0; i < n; ++i)				\
+      r[i] = a[i] == 0 ? !b[i] : a[i];			\
+  }
+
+#define TEST_ALL(T) \
+  T (int8_t) \
+  T (uint8_t) \
+  T (int16_t) \
+  T (uint16_t) \
+  T (int32_t) \
+  T (uint32_t) \
+  T (int64_t) \
+  T (uint64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
+
+/* { dg-final { scan-assembler-not {\tmov\tz} } } */
+/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
+/* Currently we canonicalize the ?: so that !b[i] is the "false" value.  */
+/* { dg-final { scan-assembler-not {\tsel\t} { xfail *-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_2_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_2_run.c
new file mode 100644
index 0000000..6db8bf1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_2_run.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target aarch64_sve_hw } } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+
+#include "cond_cnot_2.c"
+
+#define N 99
+
+#define TEST_LOOP(TYPE)						\
+  {								\
+    TYPE r[N], a[N], b[N];					\
+    for (int i = 0; i < N; ++i)					\
+      {								\
+	a[i] = (i % 3) < (i % 5);				\
+	b[i] = i % 7 < 3;					\
+	asm volatile ("" ::: "memory");				\
+      }								\
+    test_##TYPE (r, a, b, N);					\
+    for (int i = 0; i < N; ++i)					\
+      {								\
+	TYPE expected = a[i] == 0 ? !b[i] : a[i];		\
+	if (r[i] != expected)					\
+	  __builtin_abort ();					\
+	asm volatile ("" ::: "memory");				\
+      }								\
+  }
+
+int
+main (void)
+{
+  TEST_ALL (TEST_LOOP)
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_3.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_3.c
new file mode 100644
index 0000000..806e517
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_3.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+
+#include <stdint.h>
+
+#define DEF_LOOP(TYPE)					\
+  void __attribute__ ((noipa))				\
+  test_##TYPE (TYPE *__restrict r, TYPE *__restrict a,	\
+	       TYPE *__restrict b, int n)		\
+  {							\
+    for (int i = 0; i < n; ++i)				\
+      r[i] = a[i] == 0 ? !b[i] : 127;			\
+  }
+
+#define TEST_ALL(T) \
+  T (int8_t) \
+  T (uint8_t) \
+  T (int16_t) \
+  T (uint16_t) \
+  T (int32_t) \
+  T (uint32_t) \
+  T (int64_t) \
+  T (uint64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.b, p[0-7]/m,} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.h, p[0-7]/m,} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.s, p[0-7]/m,} 2 } } */
+/* { dg-final { scan-assembler-times {\tcnot\tz[0-9]+\.d, p[0-7]/m,} 2 } } */
+
+/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 8 } } */
+
+/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
+/* { dg-final { scan-assembler-not {\tsel\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_3_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_3_run.c
new file mode 100644
index 0000000..6e025e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_3_run.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target aarch64_sve_hw } } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+
+#include "cond_cnot_3.c"
+
+#define N 99
+
+#define TEST_LOOP(TYPE)						\
+  {								\
+    TYPE r[N], a[N], b[N];					\
+    for (int i = 0; i < N; ++i)					\
+      {								\
+	a[i] = (i % 3) < (i % 5);				\
+	b[i] = i % 7 < 3;					\
+	asm volatile ("" ::: "memory");				\
+      }								\
+    test_##TYPE (r, a, b, N);					\
+    for (int i = 0; i < N; ++i)					\
+      {								\
+	TYPE expected = a[i] == 0 ? !b[i] : 127;		\
+	if (r[i] != expected)					\
+	  __builtin_abort ();					\
+	asm volatile ("" ::: "memory");				\
+      }								\
+  }
+
+int
+main (void)
+{
+  TEST_ALL (TEST_LOOP)
+  return 0;
+}