mips.h (REG_ALLOC_ORDER): Put accumulators first.

gcc/
	* config/mips/mips.h (REG_ALLOC_ORDER): Put accumulators first.
	Tweak formatting.
	* config/mips/mips.c (mips_ira_cover_classes): Don't use accumulator
	registers when not optimizing.

gcc/testsuite/
	* gcc.target/mips/dspr2-MULT.c: Just check for $ac1 and $ac2.
	* gcc.target/mips/dspr2-MULTU.c: Likewise.

From-SVN: r141955

6 files changed, 34 insertions, 22 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 37bedc0..0477d27 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
 2008-11-17  Richard Sandiford  <rdsandiford@googlemail.com>
 
+	* config/mips/mips.h (REG_ALLOC_ORDER): Put accumulators first.
+	Tweak formatting.
+	* config/mips/mips.c (mips_ira_cover_classes): Don't use accumulator
+	registers when not optimizing.
+
+2008-11-17  Richard Sandiford  <rdsandiford@googlemail.com>
+
 	* config/mips/mips.md (*mul_acc_si): Remove middle alternative
 	and its associated define_split.  Expose the all-d alternative
 	to the register allocator, but mark it with "?".  Mark the first
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 5953e1a..0c2836d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9886,8 +9886,12 @@ mips_ira_cover_classes (void)
   };
 
   /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
-     which has no MTLO or MTHI instructions.  */
-  return TARGET_MIPS16 ? no_acc_classes : acc_classes;
+     which has no MTLO or MTHI instructions.  Also, using GR_AND_ACC_REGS
+     as a cover class only works well when we keep per-register costs.
+     Using it when not optimizing can cause us to think accumulators
+     have the same cost as GPRs in cases where GPRs are actually much
+     cheaper.  */
+  return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
 }
 
 /* Return the register class required for a secondary register when
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index c29c6eb..562c053 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1925,8 +1925,16 @@ enum reg_class
    call-saved ones.  (IRA expects this.)  */
 
 #define REG_ALLOC_ORDER							\
-{ /* Call-clobbered GPRs.  */						\
-   1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,		\
+{ /* Accumulator registers.  When GPRs and accumulators have equal	\
+     cost, we generally prefer to use accumulators.  For example,	\
+     a division of multiplication result is better allocated to LO,	\
+     so that we put the MFLO at the point of use instead of at the	\
+     point of definition.  It's also needed if we're to take advantage	\
+     of the extra accumulators available with -mdspr2.  In some cases,	\
+     it can also help to reduce register pressure.  */			\
+  64, 65,176,177,178,179,180,181,					\
+  /* Call-clobbered GPRs.  */						\
+  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,		\
   24, 25, 31,								\
   /* The global pointer.  This is call-clobbered for o32 and o64	\
      abicalls, call-saved for n32 and n64 abicalls, and a program	\
@@ -1936,7 +1944,7 @@ enum reg_class
   /* Call-saved GPRs.  */						\
   16, 17, 18, 19, 20, 21, 22, 23, 30,					\
   /* GPRs that can never be exposed to the register allocator.  */	\
-   0, 26, 27, 29,							\
+  0,  26, 27, 29,							\
   /* Call-clobbered FPRs.  */						\
   32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,	\
   48, 49, 50, 51,							\
@@ -1949,14 +1957,14 @@ enum reg_class
   52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,			\
   /* None of the remaining classes have defined call-saved		\
      registers.  */							\
-  64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,	\
+  66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,		\
   80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,	\
   96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111,	\
   112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,	\
   128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,	\
   144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,	\
   160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,	\
-  176,177,178,179,180,181,182,183,184,185,186,187			\
+  182,183,184,185,186,187						\
 }
 
 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 1d97976..2bc3201 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,10 @@
 2008-11-17  Richard Sandiford  <rdsandiford@googlemail.com>
 
+	* gcc.target/mips/dspr2-MULT.c: Just check for $ac1 and $ac2.
+	* gcc.target/mips/dspr2-MULTU.c: Likewise.
+
+2008-11-17  Richard Sandiford  <rdsandiford@googlemail.com>
+
 	* gcc.target/mips/madd-5.c: New test.
 	* gcc.target/mips/madd-6.c: Likewise.
 	* gcc.target/mips/madd-7.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/mips/dspr2-MULT.c b/gcc/testsuite/gcc.target/mips/dspr2-MULT.c
index bc6f3cc..9aa95c6 100644
--- a/gcc/testsuite/gcc.target/mips/dspr2-MULT.c
+++ b/gcc/testsuite/gcc.target/mips/dspr2-MULT.c
@@ -5,17 +5,11 @@
 /* { dg-final { scan-assembler "\tmult\t" } } */
 /* { dg-final { scan-assembler "ac1" } } */
 /* { dg-final { scan-assembler "ac2" } } */
-/* { dg-final { scan-assembler "ac3" } } */
 
 typedef long long a64;
-a64 a[4];
-int b[4], c[4];
 
-NOMIPS16 void test ()
+NOMIPS16 a64 test (a64 *a, int *b, int *c)
 {
   a[0] = (a64) b[0] * c[0];
   a[1] = (a64) b[1] * c[1];
-  a[2] = (a64) b[2] * c[2];
-  a[3] = (a64) b[3] * c[3];
 }
-
diff --git a/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c b/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c
index c6fef7e..ac8a7d8 100644
--- a/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c
+++ b/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c
@@ -5,17 +5,11 @@
 /* { dg-final { scan-assembler "\tmultu\t" } } */
 /* { dg-final { scan-assembler "ac1" } } */
 /* { dg-final { scan-assembler "ac2" } } */
-/* { dg-final { scan-assembler "ac3" } } */
 
-typedef long long a64;
-a64 a[4];
-unsigned int b[4], c[4];
+typedef unsigned long long a64;
 
-NOMIPS16 void test ()
+NOMIPS16 a64 test (a64 *a, unsigned int *b, unsigned int *c)
 {
   a[0] = (a64) b[0] * c[0];
   a[1] = (a64) b[1] * c[1];
-  a[2] = (a64) b[2] * c[2];
-  a[3] = (a64) b[3] * c[3];
 }
-