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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:02:54 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:02:54 -0700 |
| commit | dfa61b9ed06d71901c4c430caa89820972ad68fe (patch) | |
| tree | b6d4e739c2425a70e5b2bb5093622885b42b5af3 | |
| parent | 2e97dfdd542fba50566fd5d3dc87207d968d87d2 (diff) | |
| download | gcc-dfa61b9ed06d71901c4c430caa89820972ad68fe.zip gcc-dfa61b9ed06d71901c4c430caa89820972ad68fe.tar.gz gcc-dfa61b9ed06d71901c4c430caa89820972ad68fe.tar.bz2 | |
i386: Allow MMX register modes in SSE registers
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
PR target/89021
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE.
* config/i386/i386.c (ix86_set_reg_reg_cost): Add support for
TARGET_MMX_WITH_SSE with VALID_MMX_REG_MODE.
(ix86_vector_mode_supported_p): Likewise.
* config/i386/i386.h (TARGET_MMX_WITH_SSE): New.
From-SVN: r271213
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/i386/i386-c.c | 2 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 5 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 2 |
4 files changed, 17 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f05bd98..eb67d11 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 + * config/i386/i386-c.c (ix86_target_macros_internal): Define + __MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE. + * config/i386/i386.c (ix86_set_reg_reg_cost): Add support for + TARGET_MMX_WITH_SSE with VALID_MMX_REG_MODE. + (ix86_vector_mode_supported_p): Likewise. + * config/i386/i386.h (TARGET_MMX_WITH_SSE): New. + 2019-05-15 Martin Liska <mliska@suse.cz> PR middle-end/90478 diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 92bf066..b968bd1 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -550,6 +550,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__PTWRITE__"); if (isa_flag2 & OPTION_MASK_ISA_AVX512BF16) def_or_undef (parse_in, "__AVX512BF16__"); + if (TARGET_MMX_WITH_SSE) + def_or_undef (parse_in, "__MMX_WITH_SSE__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index cc0ae3f..4f0f5bc 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -18882,7 +18882,8 @@ ix86_set_reg_reg_cost (machine_mode mode) || (TARGET_AVX && VALID_AVX256_REG_MODE (mode)) || (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode)) || (TARGET_SSE && VALID_SSE_REG_MODE (mode)) - || (TARGET_MMX && VALID_MMX_REG_MODE (mode))) + || ((TARGET_MMX || TARGET_MMX_WITH_SSE) + && VALID_MMX_REG_MODE (mode))) units = GET_MODE_SIZE (mode); } @@ -20611,7 +20612,7 @@ ix86_vector_mode_supported_p (machine_mode mode) return true; if (TARGET_AVX512F && VALID_AVX512F_REG_MODE (mode)) return true; - if (TARGET_MMX && VALID_MMX_REG_MODE (mode)) + if ((TARGET_MMX || TARGET_MMX_WITH_SSE) && VALID_MMX_REG_MODE (mode)) return true; if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode)) return true; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 3fee779..be1480f 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -203,6 +203,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_16BIT TARGET_CODE16 #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) +#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) + #include "config/vxworks-dummy.h" #include "config/i386/i386-opts.h" |