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| author | Andrew Pinski <apinski@marvell.com> | 2022-08-19 22:09:30 +0000 |
|---|---|---|
| committer | Andrew Pinski <apinski@marvell.com> | 2022-08-24 11:30:51 -0700 |
| commit | dec5faa2b2f0d311daa6defd4b4f3c1965748ddf (patch) | |
| tree | 00a1dd71a5aa4101876b59f37b6f3b0675750483 | |
| parent | e5e6983c3da53729e58a32af1d531ea74b3dbf5d (diff) | |
| download | gcc-dec5faa2b2f0d311daa6defd4b4f3c1965748ddf.zip gcc-dec5faa2b2f0d311daa6defd4b4f3c1965748ddf.tar.gz gcc-dec5faa2b2f0d311daa6defd4b4f3c1965748ddf.tar.bz2 | |
Fix PR 106690: enable effective_target_bswap for RISCV targets with ZBB enabled by default
While looking for testcases to quickly test, I Noticed that
check_effective_target_bswap was not enabled for riscv when
ZBB is enabled. This patch checks if ZBB is enabled when
targeting RISCV* for bswap.
OK? Ran the testsuite for riscv32-linux-gnu both with and without ZBB enabled.
PR testsuite/106690
gcc/testsuite/ChangeLog:
* lib/target-supports.exp (check_effective_target_bswap):
Return true if riscv and ZBB ISA extension is enabled.
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 04a2a8e..0f1e1af 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -8646,6 +8646,13 @@ proc check_effective_target_bswap { } { || [istarget powerpc*-*-*] || [istarget rs6000-*-*] || [istarget s390*-*-*] + || ([istarget riscv*-*-*] + && [check_no_compiler_messages_nocache riscv_zbb object { + #if __riscv_zbb <= 0 + #error ZBB is not enabled + #endif + int i; + } ""]) || ([istarget arm*-*-*] && [check_no_compiler_messages_nocache arm_v6_or_later object { #if __ARM_ARCH < 6 |