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| author | Jeff Law <jlaw@ventanamicro.com> | 2025-06-27 07:00:15 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2025-06-27 07:00:15 -0600 |
| commit | de6124c9e5ed472f567b51fa76f18335cdddbbaf (patch) | |
| tree | f10dabafe3473bcf10f15f80a204e0bacf54cd95 | |
| parent | 08bdb6b4a32f1f696862db25fdcc364870b52d82 (diff) | |
| download | gcc-de6124c9e5ed472f567b51fa76f18335cdddbbaf.zip gcc-de6124c9e5ed472f567b51fa76f18335cdddbbaf.tar.gz gcc-de6124c9e5ed472f567b51fa76f18335cdddbbaf.tar.bz2 | |
[RISC-V][PR target/119971] Avoid losing shift count masking
Fix typo spotted by Bernhard Reutner-Fischer.
PR target/119971
gcc/testsuite/
* gcc.target/riscv/pr119971.c: Fix typo.
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/pr119971.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/pr119971.c b/gcc/testsuite/gcc.target/riscv/pr119971.c index c3f23b0..0d73d4c 100644 --- a/gcc/testsuite/gcc.target/riscv/pr119971.c +++ b/gcc/testsuite/gcc.target/riscv/pr119971.c @@ -1,6 +1,6 @@ /* { dg-do compile { target rv64 } } */ /* { dg-options "-march=rv64gcb -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Oz" "-Os" } } */ __attribute__ ((noipa)) unsigned foo (unsigned b, unsigned e, unsigned i) |