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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2008-12-15 21:10:00 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2008-12-15 21:10:00 +0000 |
| commit | dd021c27bfb25fa957ea4bcde302c5626d7da66b (patch) | |
| tree | 65976546ac62d5947b366b72d1e16f2f8236b488 | |
| parent | 8739b9c795cbacd63cb314aa2b265b966ad6424a (diff) | |
| download | gcc-dd021c27bfb25fa957ea4bcde302c5626d7da66b.zip gcc-dd021c27bfb25fa957ea4bcde302c5626d7da66b.tar.gz gcc-dd021c27bfb25fa957ea4bcde302c5626d7da66b.tar.bz2 | |
mips.md (move_doubleword_fpr<mode>): Use TARGET_FLOAT64 && !TARGET_64BIT to detect the mxhc1 case.
gcc/
* config/mips/mips.md (move_doubleword_fpr<mode>): Use
TARGET_FLOAT64 && !TARGET_64BIT to detect the mxhc1 case.
From-SVN: r142769
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a531498..aeed705 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2008-12-15 Richard Sandiford <rdsandiford@googlemail.com> + + * config/mips/mips.md (move_doubleword_fpr<mode>): Use + TARGET_FLOAT64 && !TARGET_64BIT to detect the mxhc1 case. + 2008-12-15 Hariharan Sandanagobalane <hariharan@picochip.com> * config/picochip/picochip.c (picochip_override_options): Disable CFI diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 1b26f02..5a06cdc 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4521,8 +4521,8 @@ rtx low = mips_subword (operands[1], 0); rtx high = mips_subword (operands[1], 1); emit_insn (gen_load_low<mode> (operands[0], low)); - if (ISA_HAS_MXHC1 && reg_or_0_operand (high, <HALFMODE>mode)) - emit_insn (gen_mthc1<mode> (operands[0], high, operands[0])); + if (TARGET_FLOAT64 && !TARGET_64BIT) + emit_insn (gen_mthc1<mode> (operands[0], high, operands[0])); else emit_insn (gen_load_high<mode> (operands[0], high, operands[0])); } @@ -4531,7 +4531,7 @@ rtx low = mips_subword (operands[0], 0); rtx high = mips_subword (operands[0], 1); emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx)); - if (ISA_HAS_MXHC1 && register_operand (high, <HALFMODE>mode)) + if (TARGET_FLOAT64 && !TARGET_64BIT) emit_insn (gen_mfhc1<mode> (high, operands[1])); else emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx)); |