c4x.md (*andqi3_255_clobber,*andqi3_65535_clobber): New logical and patterns using C40 bit-field insert instructions.

	* config/c4x/c4x.md (*andqi3_255_clobber,*andqi3_65535_clobber):
	New logical and patterns using C40 bit-field insert instructions.
	(*lshrqi3_24_clobber,*ashrqi3_24_clobber,*lshrqi3_16_clobber,
	*ashrqi3_16_clobber): New shift patterns using C40 bit-field insert
	instructions.

From-SVN: r26513

2 files changed, 77 insertions, 3 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d1b12a8..525e4b6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+Sat Apr 17 23:47:24 1999  Michael Hayes  <m.hayes@elec.canterbury.ac.nz>
+
+	* config/c4x/c4x.md (*andqi3_255_clobber,*andqi3_65535_clobber):
+	New logical and patterns using C40 bit-field insert instructions.
+	(*lshrqi3_24_clobber,*ashrqi3_24_clobber,*lshrqi3_16_clobber,
+	*ashrqi3_16_clobber): New shift patterns using C40 bit-field insert
+	instructions.
+	
 1999-04-16 22:44 -0400  Zack Weinberg  <zack@rabi.columbia.edu>
 
 	* system.h: Always prototype abort.  Prototype fatal.  Define
diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md
index 55c85d9..e7e1324 100644
--- a/gcc/config/c4x/c4x.md
+++ b/gcc/config/c4x/c4x.md
@@ -1,4 +1,4 @@
-;; Machine description for the TMS320C[34]x for GNU C compiler
+];; Machine description for the TMS320C[34]x for GNU C compiler
 ;; Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.
 
 ;; Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
@@ -2167,6 +2167,27 @@
  ""
  "legitimize_operands (AND, operands, QImode);")
 
+
+(define_insn "*andqi3_255_clobber"
+  [(set (match_operand:QI 0 "reg_operand" "=d,?c")
+        (and:QI (match_operand:QI 1 "src_operand" "mr,mr")
+                (const_int 255)))
+   (clobber (reg:CC 21))]
+ "! TARGET_C3X"
+ "lbu0\\t%1,%0"
+  [(set_attr "type" "unarycc")])
+
+
+(define_insn "*andqi3_65535_clobber"
+  [(set (match_operand:QI 0 "reg_operand" "=d,?c")
+        (and:QI (match_operand:QI 1 "src_operand" "mr,mr")
+                (const_int 65535)))
+   (clobber (reg:CC 21))]
+ "! TARGET_C3X"
+ "lhu0\\t%1,%0"
+  [(set_attr "type" "unarycc")])
+
+
 (define_insn "*andqi3_clobber"
   [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,d,c,?c,c,c")
         (and:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,0,rR,rS<>,0,0")
@@ -2513,6 +2534,47 @@
   ""
   "legitimize_operands (LSHIFTRT, operands, QImode);")
 
+
+(define_insn "*lshrqi3_24_clobber"
+  [(set (match_operand:QI 0 "reg_operand" "=d,c")
+        (lshiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
+                     (const_int 24)))
+   (clobber (reg:CC 21))]
+  "! TARGET_C3X"
+  "lbu3\\t%1,%0"
+  [(set_attr "type" "unarycc")])
+
+
+(define_insn "*ashrqi3_24_clobber"
+  [(set (match_operand:QI 0 "reg_operand" "=d,c")
+        (ashiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
+                     (const_int 24)))
+   (clobber (reg:CC 21))]
+  "! TARGET_C3X"
+  "lb3\\t%1,%0"
+  [(set_attr "type" "unarycc")])
+
+
+(define_insn "lshrqi3_16_clobber"
+  [(set (match_operand:QI 0 "reg_operand" "=d,c")
+        (lshiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
+                     (const_int 16)))
+   (clobber (reg:CC 21))]
+  "! TARGET_C3X"
+  "lhu1\\t%1,%0"
+  [(set_attr "type" "unarycc")])
+
+
+(define_insn "*ashrqi3_16_clobber"
+  [(set (match_operand:QI 0 "reg_operand" "=d,c")
+        (ashiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
+                     (const_int 16)))
+   (clobber (reg:CC 21))]
+  "! TARGET_C3X"
+  "lh1\\t%1,%0"
+  [(set_attr "type" "unarycc")])
+
+
 ; When the shift count is greater than the size of the word
 ; the result can be implementation specific
 (define_insn "*lshrqi3_const_clobber"
@@ -2874,9 +2936,11 @@
   "*
    if (INTVAL (operands[2]) == 8)
      {
+	/* 8 bit extract.  */
        operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
        return \"lbu%3\\t%1,%0\";
      }
+   /* 16 bit extract.  */
    operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
    return \"lhu%3\\t%1,%0\";
   "
@@ -2912,14 +2976,17 @@
   "*
    if (INTVAL (operands[1]) == 8)
      {
+       /* 8 bit insert.  */
        operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
        return \"mb%2\\t%3,%0\";
      }
    else if (INTVAL (operands[1]) == 16)
      {
+       /* 16 bit insert.  */
        operands[2] = GEN_INT (INTVAL (operands[2]) / 16);
        return \"mh%2\\t%3,%0\";
      }
+   /* 24 bit insert.  */
    return \"lwl1\\t%3,%0\";
   "
   [(set_attr "type" "binarycc,binary")
@@ -2948,7 +3015,7 @@
   [(set_attr "type" "binarycc")
    (set_attr "data" "uint16")])
 
-;
+
 ; TWO OPERAND FLOAT INSTRUCTIONS
 ;
 
@@ -7034,4 +7101,3 @@
  "(REGNO (operands[0]) != REGNO (operands[4]))"
  "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
 
-