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author | Nathan Sidwell <nathan@codesourcery.com> | 2009-06-22 11:54:59 +0000 |
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committer | Nathan Sidwell <nathan@gcc.gnu.org> | 2009-06-22 11:54:59 +0000 |
commit | d58bc084b4b97eb0056a2658604c855fa1775c5f (patch) | |
tree | ec049216288a8ea05bf54ad556f23b2f05c86f35 | |
parent | ac6cb60cdf1df4a9fd13f09575bdfae0d3cba87d (diff) | |
download | gcc-d58bc084b4b97eb0056a2658604c855fa1775c5f.zip gcc-d58bc084b4b97eb0056a2658604c855fa1775c5f.tar.gz gcc-d58bc084b4b97eb0056a2658604c855fa1775c5f.tar.bz2 |
arm.c (arm_print_operand): Deal with HIGH.
* config/arm/arm.c (arm_print_operand): Deal with HIGH.
* config/arm/constraints.md (j): New constraint for movw operands.
(N): Remove thumb2 meaning.
* config/arm/arm.md (*arm_movw): Delete.
(*arm_movsi_insn): Use j constraint for movw instead of N constraint.
* config/arm/vfp.md (*arm_movsi_vfp, *thumb2_movsi_vfp): Likewise.
* config/arm/thumb2.md (*thumb2_movsi_insn): Likewise.
From-SVN: r148788
-rw-r--r-- | gcc/ChangeLog | 10 | ||||
-rw-r--r-- | gcc/config/arm/arm.c | 6 | ||||
-rw-r--r-- | gcc/config/arm/arm.md | 11 | ||||
-rw-r--r-- | gcc/config/arm/constraints.md | 15 | ||||
-rw-r--r-- | gcc/config/arm/thumb2.md | 2 | ||||
-rw-r--r-- | gcc/config/arm/vfp.md | 4 |
6 files changed, 30 insertions, 18 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6a8cef5..4804cfa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2009-06-22 Nathan Sidwell <nathan@codesourcery.com> + + * config/arm/arm.c (arm_print_operand): Deal with HIGH. + * config/arm/constraints.md (j): New constraint for movw operands. + (N): Remove thumb2 meaning. + * config/arm/arm.md (*arm_movw): Delete. + (*arm_movsi_insn): Use j constraint for movw instead of N constraint. + * config/arm/vfp.md (*arm_movsi_vfp, *thumb2_movsi_vfp): Likewise. + * config/arm/thumb2.md (*thumb2_movsi_insn): Likewise. + 2009-06-22 Martin Jambor <mjambor@suse.cz> PR tree-optimization/40492 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 6f615c5..7a11d52c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -14097,6 +14097,12 @@ arm_print_operand (FILE *stream, rtx x, int code) default: gcc_assert (GET_CODE (x) != NEG); fputc ('#', stream); + if (GET_CODE (x) == HIGH) + { + fputs (":lower16:", stream); + x = XEXP (x, 0); + } + output_addr_const (stream, x); break; } diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 4797242..8423e94 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5086,18 +5086,9 @@ (set_attr "length" "4")] ) -(define_insn "*arm_movw" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r") - (high:SI (match_operand:SI 1 "general_operand" "i")))] - "TARGET_32BIT" - "movw%?\t%0, #:lower16:%c1" - [(set_attr "predicable" "yes") - (set_attr "length" "4")] -) - (define_insn "*arm_movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m") - (match_operand:SI 1 "general_operand" "rk, I,K,N,mi,rk"))] + (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk"))] "TARGET_ARM && ! TARGET_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_VFP) && ( register_operand (operands[0], SImode) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index f71599e..edb0215 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -25,7 +25,7 @@ ;; In ARM state, 'l' is an alias for 'r' ;; The following normal constraints have been used: -;; in ARM/Thumb-2 state: G, H, I, J, K, L, M +;; in ARM/Thumb-2 state: G, H, I, j, J, K, L, M ;; in Thumb-1 state: I, J, K, L, M, N, O ;; The following multi-letter normal constraints have been used: @@ -66,6 +66,13 @@ (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS" "In Thumb state the core registers @code{r8}-@code{r15}.") +(define_constraint "j" + "A constant suitable for a MOVW instruction. (ARM/Thumb-2)" + (and (match_test "TARGET_32BIT && arm_arch_thumb2") + (ior (match_code "high") + (and (match_code "const_int") + (match_test "(ival & 0xffff0000) == 0"))))) + (define_register_constraint "k" "STACK_REG" "@internal The stack register.") @@ -117,11 +124,9 @@ : ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))"))) (define_constraint "N" - "In ARM/Thumb-2 state a constant suitable for a MOVW instruction. - In Thumb-1 state a constant in the range 0-31." + "Thumb-1 state a constant in the range 0-31." (and (match_code "const_int") - (match_test "TARGET_32BIT ? arm_arch_thumb2 && ((ival & 0xffff0000) == 0) - : (ival >= 0 && ival <= 31)"))) + (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)"))) (define_constraint "O" "In Thumb-1 state a constant that is a multiple of 4 in the range diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 6ed6fb3..0c5c2db 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -225,7 +225,7 @@ (define_insn "*thumb2_movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m") - (match_operand:SI 1 "general_operand" "rk ,I,K,N,mi,rk"))] + (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,rk"))] "TARGET_THUMB2 && ! TARGET_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_VFP) && ( register_operand (operands[0], SImode) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index eb18864..06c2019 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -51,7 +51,7 @@ ;; problems because small constants get converted into adds. (define_insn "*arm_movsi_vfp" [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv") - (match_operand:SI 1 "general_operand" "rk, I,K,N,mi,rk,r,*t,*t,*Uvi,*t"))] + (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))] "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT && ( s_register_operand (operands[0], SImode) || s_register_operand (operands[1], SImode))" @@ -88,7 +88,7 @@ (define_insn "*thumb2_movsi_vfp" [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv") - (match_operand:SI 1 "general_operand" "rk, I,K,N,mi,rk,r,*t,*t,*Uvi,*t"))] + (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))] "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT && ( s_register_operand (operands[0], SImode) || s_register_operand (operands[1], SImode))" |