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| author | demin.han <demin.han@starfivetech.com> | 2023-07-27 17:48:59 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-07-27 19:41:44 +0800 |
| commit | cdc65458334faad1a2f00cf17e64e39b25d697ca (patch) | |
| tree | 445a3f8430a122ce8c338162917820e0786d146e | |
| parent | 41482832ad0aeaa0e4ae2f8d2beff17023cd00bf (diff) | |
| download | gcc-cdc65458334faad1a2f00cf17e64e39b25d697ca.zip gcc-cdc65458334faad1a2f00cf17e64e39b25d697ca.tar.gz gcc-cdc65458334faad1a2f00cf17e64e39b25d697ca.tar.bz2 | |
RISC-V: Fix uninitialized and redundant use of which_alternative
When pass split2 starts, which_alternative is random depending on
last set of certain pass.
Even initialized, the generated movement is redundant.
The movement can be generated by assembly output template.
Signed-off-by: demin.han <demin.han@starfivetech.com>
gcc/ChangeLog:
* config/riscv/autovec.md: Delete which_alternative use in split
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/madd-split2-1.c: New test.
Signed-off-by: demin.han <demin.han@starfivetech.com>
| -rw-r--r-- | gcc/config/riscv/autovec.md | 12 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c | 13 |
2 files changed, 13 insertions, 12 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index d899922..b7ea310 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1012,8 +1012,6 @@ [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (<VI:MODE>mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus (<VI:MODE>mode), riscv_vector::RVV_TERNOP, ops, operands[4]); @@ -1058,8 +1056,6 @@ [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (<VI:MODE>mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (<VI:MODE>mode), riscv_vector::RVV_TERNOP, ops, operands[4]); @@ -1102,8 +1098,6 @@ [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (PLUS, <VF:MODE>mode), riscv_vector::RVV_TERNOP, ops, operands[4]); @@ -1148,8 +1142,6 @@ [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (PLUS, <VF:MODE>mode), riscv_vector::RVV_TERNOP, ops, operands[4]); @@ -1194,8 +1186,6 @@ [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (MINUS, <VF:MODE>mode), riscv_vector::RVV_TERNOP, ops, operands[4]); @@ -1242,8 +1232,6 @@ [(const_int 0)] { riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]); - if (which_alternative == 2) - emit_insn (gen_rtx_SET (operands[0], operands[3])); rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (MINUS, <VF:MODE>mode), riscv_vector::RVV_TERNOP, ops, operands[4]); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c new file mode 100644 index 0000000..14a9802 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */ + +long +foo (long *__restrict a, long *__restrict b, long n) +{ + long i; + for (i = 0; i < n; ++i) + a[i] = b[i] + i * 8; + return a[1]; +} + +/* { dg-final { scan-assembler-times {\tvmv1r\.v} 1 } } */ |