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| author | Andrew Pinski <apinski@marvell.com> | 2022-08-19 17:01:02 +0000 |
|---|---|---|
| committer | Andrew Pinski <apinski@marvell.com> | 2022-08-24 11:30:30 -0700 |
| commit | cb2daf5acce003300ee948a89860c0d13ebcae79 (patch) | |
| tree | 9fdda731ff892230b69b1e09b1f20590f7af6546 | |
| parent | 55d8c5409325001c89c35c3d04d425dec9127146 (diff) | |
| download | gcc-cb2daf5acce003300ee948a89860c0d13ebcae79.zip gcc-cb2daf5acce003300ee948a89860c0d13ebcae79.tar.gz gcc-cb2daf5acce003300ee948a89860c0d13ebcae79.tar.bz2 | |
Fix PR 106600: __builtin_bswap32 is not hooked up for ZBB for 32bit
The problem here is the bswap<mode>2 pattern had a check for TARGET_64BIT
but then used the X iterator. Since the X iterator is either SI or DI depending
on the setting TARGET_64BIT, there is no reason for the TARGET_64BIT.
OK? Built and tested on both riscv32-linux-gnu and riscv64-linux-gnu.
Thanks,
Andrew Pinski
gcc/ChangeLog:
PR target/106600
* config/riscv/bitmanip.md (bswap<mode>2): Remove
condition on TARGET_64BIT as X is already conditional there.
gcc/testsuite/ChangeLog:
PR target/106600
* gcc.target/riscv/zbb_32_bswap-1.c: New test.
* gcc.target/riscv/zbb_bswap-1.c: New test.
| -rw-r--r-- | gcc/config/riscv/bitmanip.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c | 11 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c | 11 |
3 files changed, 23 insertions, 1 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index d1570ce..c7ba667 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -272,7 +272,7 @@ (define_insn "bswap<mode>2" [(set (match_operand:X 0 "register_operand" "=r") (bswap:X (match_operand:X 1 "register_operand" "r")))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_ZBB" "rev8\t%0,%1" [(set_attr "type" "bitmanip")]) diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c new file mode 100644 index 0000000..3ff7d9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +int foo(int n) +{ + return __builtin_bswap32(n); +} + +/* { dg-final { scan-assembler "rev8" } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c b/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c new file mode 100644 index 0000000..20feded --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +int foo(int n) +{ + return __builtin_bswap32(n); +} + +/* { dg-final { scan-assembler "rev8" } } */ + |