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| author | Lehua Ding <lehua.ding@rivai.ai> | 2023-08-17 15:42:51 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-08-18 10:29:44 +0800 |
| commit | c43916857c6586e65f10713fdc5a65909918a8cc (patch) | |
| tree | e0aa18db834b1854bd9ed71dd31f50d16eb06922 | |
| parent | 1eb2433ff9e85008a289db03ff7eb802d51c42a8 (diff) | |
| download | gcc-c43916857c6586e65f10713fdc5a65909918a8cc.zip gcc-c43916857c6586e65f10713fdc5a65909918a8cc.tar.gz gcc-c43916857c6586e65f10713fdc5a65909918a8cc.tar.bz2 | |
RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl
Hi,
This little patch fix the fail testcase
(gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c)
after apply this patch
(https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627121.html).
The specific reason is that the vsetvl pass has bug and this patch
forbidden the fuse of this case. This patch needs to be committed
before that patch to work.
Best,
Lehua
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::backward_demand_fusion):
Forbidden.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c:
Address failure due to uninitialized vtype register.
| -rw-r--r-- | gcc/config/riscv/riscv-vsetvl.cc | 17 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c | 6 |
2 files changed, 23 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 79cbac0..2d8fa75 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -3330,6 +3330,23 @@ pass_vsetvl::backward_demand_fusion (void) else if (block_info.reaching_out.dirty_p ()) { /* DIRTY -> DIRTY or VALID -> DIRTY. */ + + /* Forbidden this case fuse because it change the value of a5. + bb 1: vsetvl zero, no_zero_avl + ... + use a5 + ... + bb 2: vsetvl a5, zero + => + bb 1: vsetvl a5, zero + ... + use a5 + ... + bb 2: + */ + if (block_info.reaching_out.demand_p (DEMAND_NONZERO_AVL) + && vlmax_avl_p (prop.get_avl ())) + continue; vector_insn_info new_info; if (block_info.reaching_out.compatible_p (prop)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c index 7ffa93b..7eeb22a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c @@ -7,6 +7,12 @@ int main (void) { + /* FIXME: The purpose of this assembly is to ensure that the vtype register is + initialized befor instructions such as vmv1r.v are executed. Otherwise you + will get illegal instruction errors when running with spike+pk. This is an + interim solution for reduce unnecessary failures and a unified solution + will come later. */ + asm volatile("vsetivli x0, 0, e8, m1, ta, ma"); #define RUN_LOOP(DATA_TYPE, BITS) \ DATA_TYPE dest_##DATA_TYPE##_##BITS[(BITS - 3) * (BITS + 13)]; \ DATA_TYPE dest2_##DATA_TYPE##_##BITS[(BITS - 3) * (BITS + 13)]; \ |