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| author | Shiva Chen <shiva0217@gmail.com> | 2018-04-22 09:05:10 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gcc.gnu.org> | 2018-04-22 09:05:10 +0000 |
| commit | c411e9aa4fd63e03a8e4594776ceb22ff3966dbc (patch) | |
| tree | 18c910d33e9b81820e865510cc9a238f2e9d8e0a | |
| parent | 029db20edd88bf6aa038cc949f70ba5c3890a5fc (diff) | |
| download | gcc-c411e9aa4fd63e03a8e4594776ceb22ff3966dbc.zip gcc-c411e9aa4fd63e03a8e4594776ceb22ff3966dbc.tar.gz gcc-c411e9aa4fd63e03a8e4594776ceb22ff3966dbc.tar.bz2 | |
[NDS32] Implment USE_LOAD_POST_INCREMENT, USE_LOAD_POST_DECREMENT, USE_STORE_POST_DECREMENT and USE_STORE_POST_INCREMENT.
gcc/
* config/nds32/nds32-protos.h (nds32_use_load_post_increment): Declare.
* config/nds32/nds32.c (nds32_use_load_post_increment): New.
* config/nds32/nds32.h
(USE_LOAD_POST_INCREMENT, USE_LOAD_POST_DECREMENT): Define.
(USE_STORE_POST_INCREMENT, USE_STORE_POST_DECREMENT): Define.
From-SVN: r259552
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32-protos.h | 2 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32.c | 8 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32.h | 6 |
4 files changed, 24 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d84f5bc..3aa5542 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2018-04-22 Shiva Chen <shiva0217@gmail.com> + * config/nds32/nds32-protos.h (nds32_use_load_post_increment): Declare. + * config/nds32/nds32.c (nds32_use_load_post_increment): New. + * config/nds32/nds32.h + (USE_LOAD_POST_INCREMENT, USE_LOAD_POST_DECREMENT): Define. + (USE_STORE_POST_INCREMENT, USE_STORE_POST_DECREMENT): Define. + +2018-04-22 Shiva Chen <shiva0217@gmail.com> + * config/nds32/nds32-protos.h (nds32_ls_333_p): Remove. * config/nds32/nds32.c (nds32_ls_333_p): Remove. diff --git a/gcc/config/nds32/nds32-protos.h b/gcc/config/nds32/nds32-protos.h index 7e8111e..e7b7d41 100644 --- a/gcc/config/nds32/nds32-protos.h +++ b/gcc/config/nds32/nds32-protos.h @@ -275,6 +275,8 @@ rtx extract_branch_target_rtx (rtx_insn *); rtx extract_branch_condition_rtx (rtx_insn *); } // namespace nds32 +extern bool nds32_use_load_post_increment(machine_mode); + /* Functions for create nds32 specific optimization pass. */ extern rtl_opt_pass *make_pass_nds32_relax_opt (gcc::context *); diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c index 997cc76..9a8c712 100644 --- a/gcc/config/nds32/nds32.c +++ b/gcc/config/nds32/nds32.c @@ -1354,6 +1354,14 @@ nds32_naked_function_p (tree func) return (t != NULL_TREE); } +/* Function that determine whether a load postincrement is a good thing to use + for a given mode. */ +bool +nds32_use_load_post_increment (machine_mode mode) +{ + return (GET_MODE_SIZE (mode) <= GET_MODE_SIZE(E_DImode)); +} + /* Function that check if 'X' is a valid address register. The variable 'STRICT' is very important to make decision for register number. diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h index c5d1e27..29edccd 100644 --- a/gcc/config/nds32/nds32.h +++ b/gcc/config/nds32/nds32.h @@ -1083,6 +1083,12 @@ enum reg_class /* We have "LW.bi Rt, [Ra], Rb" instruction form. */ #define HAVE_POST_MODIFY_REG 1 +#define USE_LOAD_POST_INCREMENT(mode) \ + nds32_use_load_post_increment(mode) +#define USE_LOAD_POST_DECREMENT(mode) USE_LOAD_POST_INCREMENT(mode) +#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) +#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) + #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE) #define MAX_REGS_PER_ADDRESS 3 |