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author | H.J. Lu <hongjiu.lu@intel.com> | 2018-10-21 10:35:36 +0000 |
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committer | H.J. Lu <hjl@gcc.gnu.org> | 2018-10-21 03:35:36 -0700 |
commit | c038638ea9dfc75fac9559cdb035754af85960d0 (patch) | |
tree | cfdd6636246eead93006c5b22d3c019f1023ae58 | |
parent | 01fd9f8d21c8bc0fe818238177e98fd84591b61f (diff) | |
download | gcc-c038638ea9dfc75fac9559cdb035754af85960d0.zip gcc-c038638ea9dfc75fac9559cdb035754af85960d0.tar.gz gcc-c038638ea9dfc75fac9559cdb035754af85960d0.tar.bz2 |
i386: Enable AVX512 memory broadcast for FP mul
Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for FP mul operations.
gcc/
PR target/72782
* config/i386/sse.md (*mul<mode>3<mask_name>_bcst): New.
gcc/testsuite/
PR target/72782
* gcc.target/i386/avx512f-mul-df-zmm-1.c: New test.
* gcc.target/i386/avx512f-mul-sf-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-mul-sf-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-mul-sf-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-mul-sf-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-mul-sf-zmm-5.c: Likewise.
* gcc.target/i386/avx512f-mul-sf-zmm-6.c: Likewise.
* gcc.target/i386/avx512vl-mul-sf-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-mul-sf-ymm-1.c: Likewise.
From-SVN: r265351
-rw-r--r-- | gcc/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/config/i386/sse.md | 12 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 13 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512f-mul-df-zmm-1.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-1.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-2.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-3.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-4.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-5.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-6.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512vl-mul-sf-xmm-1.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512vl-mul-sf-ymm-1.c | 12 |
12 files changed, 138 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4d85691..d4ce806 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2018-10-21 H.J. Lu <hongjiu.lu@intel.com> + PR target/72782 + * config/i386/sse.md (*mul<mode>3<mask_name>_bcst): New. + +2018-10-21 H.J. Lu <hongjiu.lu@intel.com> + PR target/87662 * i386/avx512vlintrin.h (_mm256_or_epi32): New. (_mm_or_epi32): Likewise. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1b41aa5..f29ee9d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1754,6 +1754,18 @@ (set_attr "btver2_decode" "direct,double") (set_attr "mode" "<MODE>")]) +(define_insn "*mul<mode>3<mask_name>_bcst" + [(set (match_operand:VF_AVX512 0 "register_operand" "=v") + (mult:VF_AVX512 + (vec_duplicate:VF_AVX512 + (match_operand:<ssescalarmode> 1 "memory_operand" "m")) + (match_operand:VF_AVX512 2 "register_operand" "v")))] + "TARGET_AVX512F && <mask_mode512bit_condition>" + "vmul<ssemodesuffix>\t{%1<avx512bcst>, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1<<avx512bcst>>}" + [(set_attr "prefix" "evex") + (set_attr "type" "ssemul") + (set_attr "mode" "<MODE>")]) + (define_insn "<sse>_vm<multdiv_mnemonic><mode>3<mask_scalar_name><round_scalar_name>" [(set (match_operand:VF_128 0 "register_operand" "=x,v") (vec_merge:VF_128 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c0d1ad2..6e1c684 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,18 @@ 2018-10-21 H.J. Lu <hongjiu.lu@intel.com> + PR target/72782 + * gcc.target/i386/avx512f-mul-df-zmm-1.c: New test. + * gcc.target/i386/avx512f-mul-sf-zmm-1.c: Likewise. + * gcc.target/i386/avx512f-mul-sf-zmm-2.c: Likewise. + * gcc.target/i386/avx512f-mul-sf-zmm-3.c: Likewise. + * gcc.target/i386/avx512f-mul-sf-zmm-4.c: Likewise. + * gcc.target/i386/avx512f-mul-sf-zmm-5.c: Likewise. + * gcc.target/i386/avx512f-mul-sf-zmm-6.c: Likewise. + * gcc.target/i386/avx512vl-mul-sf-xmm-1.c: Likewise. + * gcc.target/i386/avx512vl-mul-sf-ymm-1.c: Likewise. + +2018-10-21 H.J. Lu <hongjiu.lu@intel.com> + PR target/87662 * gcc.target/i386/pr87662.c diff --git a/gcc/testsuite/gcc.target/i386/avx512f-mul-df-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-mul-df-zmm-1.c new file mode 100644 index 0000000..e3c5198 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-mul-df-zmm-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vmulpd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vbroadcastsd\[^\n\]*%zmm\[0-9\]+" } } */ + +#define type __m512d +#define vec 512 +#define op mul +#define suffix pd +#define SCALAR double + +#include "avx512-binop-1.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-1.c new file mode 100644 index 0000000..14bccca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%zmm\[0-9\]+" } } */ + +#define type __m512 +#define vec 512 +#define op mul +#define suffix ps +#define SCALAR float + +#include "avx512-binop-1.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-2.c new file mode 100644 index 0000000..8293324 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%zmm\[0-9\]+" } } */ + +#define type __m512 +#define vec 512 +#define op mul +#define suffix ps +#define SCALAR float + +#include "avx512-binop-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-3.c new file mode 100644 index 0000000..cb768db --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vmulps\[^\n\]*%zmm\[0-9\]+" 1 } } */ + +#define type __m512 +#define vec 512 +#define op mul +#define suffix ps +#define SCALAR float + +#include "avx512-binop-3.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-4.c new file mode 100644 index 0000000..7626192 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */ + +#define type __m512 +#define vec 512 +#define op mul +#define suffix ps +#define SCALAR float + +#include "avx512-binop-4.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-5.c new file mode 100644 index 0000000..b2ad805 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%zmm\[0-9\]+" } } */ + +#define type __m512 +#define vec 512 +#define op mul +#define suffix ps +#define SCALAR float + +#include "avx512-binop-5.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-6.c b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-6.c new file mode 100644 index 0000000..d8dde86 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-mul-sf-zmm-6.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%zmm\[0-9\]+" } } */ + +#define type __m512 +#define vec 512 +#define op mul +#define suffix ps +#define SCALAR float + +#include "avx512-binop-6.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-mul-sf-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-mul-sf-xmm-1.c new file mode 100644 index 0000000..bbb0041 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-mul-sf-xmm-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%xmm\[0-9\]+" } } */ + +#define type __m128 +#define vec +#define op mul +#define suffix ps +#define SCALAR float + +#include "avx512-binop-1.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-mul-sf-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-mul-sf-ymm-1.c new file mode 100644 index 0000000..35810b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-mul-sf-ymm-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */ +/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%ymm\[0-9\]+" } } */ + +#define type __m256 +#define vec 256 +#define op mul +#define suffix ps +#define SCALAR float + +#include "avx512-binop-1.h" |