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| author | Chung-Ju Wu <jasonwucj@gmail.com> | 2018-04-05 03:10:42 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gcc.gnu.org> | 2018-04-05 03:10:42 +0000 |
| commit | b9774a97af284e42882cd30b7ba352e3dea8c9ed (patch) | |
| tree | 6900855552e34f92d7b6834b0c15e0794d06d875 | |
| parent | 50ea1e4ad5f0b926799f935115dcdcb128a4764e (diff) | |
| download | gcc-b9774a97af284e42882cd30b7ba352e3dea8c9ed.zip gcc-b9774a97af284e42882cd30b7ba352e3dea8c9ed.tar.gz gcc-b9774a97af284e42882cd30b7ba352e3dea8c9ed.tar.bz2 | |
[NDS32] Generate alu-shift instructions only for -Os.
gcc/
* config/nds32/nds32.md: Use optimize_size in the condition for
alu-shift instructions.
From-SVN: r259120
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32.md | 20 |
2 files changed, 15 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 485c59e..0928418 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com> + * config/nds32/nds32.md: Use optimize_size in the condition for + alu-shift instructions. + +2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com> + * config/nds32/nds32.md (divsi4, udivsi4): New patterns. 2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com> diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index 2d0f1d3..b64e1c2 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -385,7 +385,7 @@ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "immediate_operand" " i")) (match_operand:SI 3 "register_operand" " r")))] - "TARGET_ISA_V3 + "TARGET_ISA_V3 && optimize_size && (exact_log2 (INTVAL (operands[2])) != -1) && (exact_log2 (INTVAL (operands[2])) <= 31)" { @@ -404,7 +404,7 @@ (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "nds32_imm5u_operand" " Iu05")) (match_operand:SI 3 "register_operand" " r")))] - "TARGET_ISA_V3" + "TARGET_ISA_V3 && optimize_size" "add_srli\t%0, %3, %1, %2" [(set_attr "type" "alu_shift") (set_attr "combo" "2") @@ -419,7 +419,7 @@ (minus:SI (match_operand:SI 1 "register_operand" " r") (mult:SI (match_operand:SI 2 "register_operand" " r") (match_operand:SI 3 "immediate_operand" " i"))))] - "TARGET_ISA_V3 + "TARGET_ISA_V3 && optimize_size && (exact_log2 (INTVAL (operands[3])) != -1) && (exact_log2 (INTVAL (operands[3])) <= 31)" { @@ -438,7 +438,7 @@ (minus:SI (match_operand:SI 1 "register_operand" " r") (lshiftrt:SI (match_operand:SI 2 "register_operand" " r") (match_operand:SI 3 "nds32_imm5u_operand" " Iu05"))))] - "TARGET_ISA_V3" + "TARGET_ISA_V3 && optimize_size" "sub_srli\t%0, %1, %2, %3" [(set_attr "type" "alu_shift") (set_attr "combo" "2") @@ -650,7 +650,7 @@ (and:SI (ashift:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "nds32_imm5u_operand" " Iu05")) (match_operand:SI 3 "register_operand" " r")))] - "TARGET_ISA_V3" + "TARGET_ISA_V3 && optimize_size" "and_slli\t%0, %3, %1, %2" [(set_attr "type" "alu_shift") (set_attr "length" "4")]) @@ -660,7 +660,7 @@ (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "nds32_imm5u_operand" " Iu05")) (match_operand:SI 3 "register_operand" " r")))] - "TARGET_ISA_V3" + "TARGET_ISA_V3 && optimize_size" "and_srli\t%0, %3, %1, %2" [(set_attr "type" "alu_shift") (set_attr "length" "4")]) @@ -702,7 +702,7 @@ (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "nds32_imm5u_operand" " Iu05")) (match_operand:SI 3 "register_operand" " r")))] - "TARGET_ISA_V3" + "TARGET_ISA_V3 && optimize_size" "or_slli\t%0, %3, %1, %2" [(set_attr "type" "alu_shift") (set_attr "length" "4")]) @@ -712,7 +712,7 @@ (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "nds32_imm5u_operand" " Iu05")) (match_operand:SI 3 "register_operand" " r")))] - "TARGET_ISA_V3" + "TARGET_ISA_V3 && optimize_size" "or_srli\t%0, %3, %1, %2" [(set_attr "type" "alu_shift") (set_attr "length" "4")]) @@ -754,7 +754,7 @@ (xor:SI (ashift:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "nds32_imm5u_operand" " Iu05")) (match_operand:SI 3 "register_operand" " r")))] - "TARGET_ISA_V3" + "TARGET_ISA_V3 && optimize_size" "xor_slli\t%0, %3, %1, %2" [(set_attr "type" "alu_shift") (set_attr "length" "4")]) @@ -764,7 +764,7 @@ (xor:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "nds32_imm5u_operand" " Iu05")) (match_operand:SI 3 "register_operand" " r")))] - "TARGET_ISA_V3" + "TARGET_ISA_V3 && optimize_size" "xor_srli\t%0, %3, %1, %2" [(set_attr "type" "alu_shift") (set_attr "length" "4")]) |