diff options
| author | Carl Love <cel@us.ibm.com> | 2018-05-16 17:21:04 +0000 |
|---|---|---|
| committer | Carl Love <carll@gcc.gnu.org> | 2018-05-16 17:21:04 +0000 |
| commit | b958e1c134344ea06aa53ba0ca0935363ed3a8e8 (patch) | |
| tree | 08b23e9ecb41f589ccab68f94f4a82383d79009b | |
| parent | 73264a8d66c00162103e39b46cd388a4f566821c (diff) | |
| download | gcc-b958e1c134344ea06aa53ba0ca0935363ed3a8e8.zip gcc-b958e1c134344ea06aa53ba0ca0935363ed3a8e8.tar.gz gcc-b958e1c134344ea06aa53ba0ca0935363ed3a8e8.tar.bz2 | |
rs6000.md (prefetch): Generate ISA 2.06 instructions dcbt and dcbtstt with TH=16 if...
gcc/ChangeLog:
2018-05-16 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000.md (prefetch): Generate ISA 2.06 instructions
dcbt and dcbtstt with TH=16 if operands[2] is 0 and Power 8 or newer.
From-SVN: r260296
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 17 |
2 files changed, 16 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8a84812..59c4b42 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-05-16 Carl Love <cel@us.ibm.com> + + * config/rs6000/rs6000.md (prefetch): Generate ISA 2.06 instructions + dcbt and dcbtstt with TH=16 if operands[2] is 0 and Power 8 or newer. + 2018-05-16 Martin Jambor <mjambor@suse.cz> * ipa-prop.c (ipa_free_all_edge_args): Remove. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b249a1f..6d8e5e2 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -13243,22 +13243,27 @@ (match_operand:SI 2 "const_int_operand" "n"))] "" { - /* dcbtstt, dcbtt and TM=0b10000 support starts with ISA 2.06. */ - int inst_select = INTVAL (operands[2]) || !TARGET_POPCNTD; + + + /* dcbtstt, dcbtt and TH=0b10000 support starts with ISA 2.06 (Power7). + AIX does not support the dcbtstt and dcbtt extended mnemonics. + The AIX assembler does not support the three operand form of dcbt + and dcbtst on Power 7 (-mpwr7). */ + int inst_select = INTVAL (operands[2]) || !TARGET_DIRECT_MOVE; if (REG_P (operands[0])) { if (INTVAL (operands[1]) == 0) - return inst_select ? "dcbt 0,%0" : "dcbtt 0,%0"; + return inst_select ? "dcbt 0,%0" : "dcbt 0,%0,16"; else - return inst_select ? "dcbtst 0,%0" : "dcbtstt 0,%0"; + return inst_select ? "dcbtst 0,%0" : "dcbtst 0,%0,16"; } else { if (INTVAL (operands[1]) == 0) - return inst_select ? "dcbt %a0" : "dcbtt %a0"; + return inst_select ? "dcbt %a0" : "dcbt %a0,16"; else - return inst_select ? "dcbtst %a0" : "dcbtstt %a0"; + return inst_select ? "dcbtst %a0" : "dcbtst %a0,16"; } } [(set_attr "type" "load")]) |