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| author | Richard Henderson <rth@redhat.com> | 2002-03-17 19:06:05 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2002-03-17 19:06:05 -0800 |
| commit | b83b7fa3716d7327fe5c0ed16de166e5816f7d9f (patch) | |
| tree | be1d934eb1e426d7de725a8edd056e16cfb5d3bc | |
| parent | 6f7c00fe3423564af915f47b79bab7b28dcbb158 (diff) | |
| download | gcc-b83b7fa3716d7327fe5c0ed16de166e5816f7d9f.zip gcc-b83b7fa3716d7327fe5c0ed16de166e5816f7d9f.tar.gz gcc-b83b7fa3716d7327fe5c0ed16de166e5816f7d9f.tar.bz2 | |
alpha.c (alpha_emit_set_const_1): Build add insns explicitly.
* config/alpha/alpha.c (alpha_emit_set_const_1): Build add insns
explicitly.
From-SVN: r50942
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.c | 25 |
2 files changed, 25 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index acd64f1..673a79e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2002-03-17 Richard Henderson <rth@redhat.com> + + * config/alpha/alpha.c (alpha_emit_set_const_1): Build add insns + explicitly. + 2002-03-17 Hans-Peter Nilsson <hp@bitrange.com> * config/mmix/mmix.md ("fixuns_truncdfdi2"): Use (unsigned_fix:DI diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index ed25a7d..08f4568 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -2274,7 +2274,7 @@ alpha_emit_set_const_1 (target, mode, c, n) /* Use a pseudo if highly optimizing and still generating RTL. */ rtx subtarget = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target); - rtx temp; + rtx temp, insn; #if HOST_BITS_PER_WIDE_INT == 64 /* We are only called for SImode and DImode. If this is SImode, ensure that @@ -2324,12 +2324,27 @@ alpha_emit_set_const_1 (target, mode, c, n) { temp = copy_to_suggested_reg (GEN_INT (high << 16), subtarget, mode); + /* As of 2002-02-23, addsi3 is only available when not optimizing. + This means that if we go through expand_binop, we'll try to + generate extensions, etc, which will require new pseudos, which + will fail during some split phases. The SImode add patterns + still exist, but are not named. So build the insns by hand. */ + if (extra != 0) - temp = expand_binop (mode, add_optab, temp, GEN_INT (extra << 16), - subtarget, 0, OPTAB_WIDEN); + { + if (! subtarget) + subtarget = gen_reg_rtx (mode); + insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16)); + insn = gen_rtx_SET (VOIDmode, subtarget, insn); + emit_insn (insn); + } - return expand_binop (mode, add_optab, temp, GEN_INT (low), - target, 0, OPTAB_WIDEN); + if (target == NULL) + target = gen_reg_rtx (mode); + insn = gen_rtx_PLUS (mode, temp, GEN_INT (low)); + insn = gen_rtx_SET (VOIDmode, target, insn); + emit_insn (insn); + return target; } } |