diff options
author | Pan Li <pan2.li@intel.com> | 2025-05-03 11:37:09 +0800 |
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committer | Pan Li <pan2.li@intel.com> | 2025-05-06 20:31:55 +0800 |
commit | b3a32804bebb9520b327b7cbf3e8f8b4730f9bd6 (patch) | |
tree | 00c89ab6353bd13feea050a333f9c801b01c8799 | |
parent | c10491efc108bd4fc2d983bcabb50506d09e2a17 (diff) | |
download | gcc-b3a32804bebb9520b327b7cbf3e8f8b4730f9bd6.zip gcc-b3a32804bebb9520b327b7cbf3e8f8b4730f9bd6.tar.gz gcc-b3a32804bebb9520b327b7cbf3e8f8b4730f9bd6.tar.bz2 |
RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 15
Add asm dump check and for vec_duplicate + vadd.vv combine to vadd.vx.
The late-combine will not take action when GR2VR cost is 15.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
8 files changed, 64 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c new file mode 100644 index 0000000..f3a2627 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int16_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c new file mode 100644 index 0000000..490854c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int32_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c new file mode 100644 index 0000000..a7448df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int64_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c new file mode 100644 index 0000000..72c7cd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(int8_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c new file mode 100644 index 0000000..552b4ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint16_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c new file mode 100644 index 0000000..e319672 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint32_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c new file mode 100644 index 0000000..6e2a89e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint64_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c new file mode 100644 index 0000000..d3383e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY(uint8_t, +) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ |