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| author | Andrew Pinski <quic_apinski@quicinc.com> | 2024-11-21 10:51:38 -0800 |
|---|---|---|
| committer | Andrew Pinski <quic_apinski@quicinc.com> | 2024-11-29 12:09:10 -0800 |
| commit | b35f9c2535a34279898bf8795e748161fd1704ed (patch) | |
| tree | 51424ce88b1e8a64d3e0aa41e2fa5bce23a542fc | |
| parent | af974df94751195ce72e86d7b88e5d5444375b45 (diff) | |
| download | gcc-b35f9c2535a34279898bf8795e748161fd1704ed.zip gcc-b35f9c2535a34279898bf8795e748161fd1704ed.tar.gz gcc-b35f9c2535a34279898bf8795e748161fd1704ed.tar.bz2 | |
aarch64: Fix up flags for vget_low_*, vget_high_* and vreinterpret intrinsics
These 3 intrinsics will not raise an fp exception, or read FPCR. These intrinsics,
will be folded into VIEW_CONVERT_EXPR or a BIT_FIELD_REF which is already set to
be const expressions too.
Built and tested for aarch64-linux-gnu.
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc (VREINTERPRET_BUILTIN): Use
FLAG_NONE instead of FLAG_AUTO_FP.
(VGET_LOW_BUILTIN): Likewise.
(VGET_HIGH_BUILTIN): Likewise.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
| -rw-r--r-- | gcc/config/aarch64/aarch64-builtins.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index e26ee32..04ae16a 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -911,7 +911,7 @@ static aarch64_fcmla_laneq_builtin_datum aarch64_fcmla_lane_builtin_data[] = { 2, \ { SIMD_INTR_MODE(A, L), SIMD_INTR_MODE(B, L) }, \ { SIMD_INTR_QUAL(A), SIMD_INTR_QUAL(B) }, \ - FLAG_AUTO_FP, \ + FLAG_NONE, \ SIMD_INTR_MODE(A, L) == SIMD_INTR_MODE(B, L) \ && SIMD_INTR_QUAL(A) == SIMD_INTR_QUAL(B) \ }, @@ -923,7 +923,7 @@ static aarch64_fcmla_laneq_builtin_datum aarch64_fcmla_lane_builtin_data[] = { 2, \ { SIMD_INTR_MODE(A, d), SIMD_INTR_MODE(A, q) }, \ { SIMD_INTR_QUAL(A), SIMD_INTR_QUAL(A) }, \ - FLAG_AUTO_FP, \ + FLAG_NONE, \ false \ }, @@ -934,7 +934,7 @@ static aarch64_fcmla_laneq_builtin_datum aarch64_fcmla_lane_builtin_data[] = { 2, \ { SIMD_INTR_MODE(A, d), SIMD_INTR_MODE(A, q) }, \ { SIMD_INTR_QUAL(A), SIMD_INTR_QUAL(A) }, \ - FLAG_AUTO_FP, \ + FLAG_NONE, \ false \ }, |