h8300-protos.h: Add a prototype for iorxor_operator.

	* config/h8300/h8300-protos.h: Add a prototype for
	iorxor_operator.
	* config/h8300/h8300.c (print_operand): Handle 'c'.
	(iorxor_operator): New.
	* config/h8300/h8300.h (PREDICATE_CODES): Add iorxor_operator.
	* config/h8300/h8300.md (*iorhi3_zext): Remove.
	(*iorsi3_zexthi): Likewise.
	(*iorsi3_zextsi): Likewise.
	(*xorhi3_zextqi): Likewise.
	(*xorsi3_zexthi): Likewise.
	(*xorsi3_zextsi): Likewise.
	(*ixorhi3_zext): New.
	(*ixorsi3_zext_qi): Likewise.
	(*ixorsi3_zext_hi): Likewise.

From-SVN: r63671

5 files changed, 76 insertions, 55 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index de9440f..289cb4b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2003-03-02  Kazu Hirata  <kazu@cs.umass.edu>
+
+	* config/h8300/h8300-protos.h: Add a prototype for
+	iorxor_operator.
+	* config/h8300/h8300.c (print_operand): Handle 'c'.
+	(iorxor_operator): New.
+	* config/h8300/h8300.h (PREDICATE_CODES): Add iorxor_operator.
+	* config/h8300/h8300.md (*iorhi3_zext): Remove.
+	(*iorsi3_zexthi): Likewise.
+	(*iorsi3_zextsi): Likewise.
+	(*xorhi3_zextqi): Likewise.
+	(*xorsi3_zexthi): Likewise.
+	(*xorsi3_zextsi): Likewise.
+	(*ixorhi3_zext): New.
+	(*ixorsi3_zext_qi): Likewise.
+	(*ixorsi3_zext_hi): Likewise.
+
 2003-03-02  Neil Booth  <neil@daikokuya.co.uk>
 
 	* c-incpath.c (remove_component_p, simplify_path): Move back to
diff --git a/gcc/config/h8300/h8300-protos.h b/gcc/config/h8300/h8300-protos.h
index 6c2fe68..57f047f 100644
--- a/gcc/config/h8300/h8300-protos.h
+++ b/gcc/config/h8300/h8300-protos.h
@@ -69,6 +69,7 @@ extern int bit_operator PARAMS ((rtx, enum machine_mode));
 extern int nshift_operator PARAMS ((rtx, enum machine_mode));
 extern int eqne_operator PARAMS ((rtx, enum machine_mode));
 extern int gtuleu_operator PARAMS ((rtx, enum machine_mode));
+extern int iorxor_operator PARAMS ((rtx, enum machine_mode));
 
 extern int h8300_eightbit_constant_address_p PARAMS ((rtx));
 extern int h8300_tiny_constant_address_p PARAMS ((rtx));
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index ef9dbdd..79ec178 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -1238,6 +1238,7 @@ h8300_rtx_costs (x, code, outer_code, total)
        If this operand isn't a register, fall back to 'R' handling.
    'Z' print int & 7.
    'b' print the bit opcode
+   'c' print the opcode corresponding to rtl
    'e' first word of 32 bit value - if reg, then least reg. if mem
        then least. if const then most sig word
    'f' second word of 32 bit value - if reg, then biggest reg. if mem
@@ -1390,6 +1391,19 @@ print_operand (file, x, code)
 	  break;
 	}
       break;
+    case 'c':
+      switch (GET_CODE (x))
+	{
+	case IOR:
+	  fprintf (file, "or");
+	  break;
+	case XOR:
+	  fprintf (file, "xor");
+	  break;
+	default:
+	  break;
+	}
+      break;
     case 'e':
       switch (GET_CODE (x))
 	{
@@ -1903,6 +1917,18 @@ gtuleu_operator (x, mode)
   return (code == GTU || code == LEU);
 }
 
+/* Return nonzero if X is either IOR or XOR.  */
+
+int
+iorxor_operator (x, mode)
+     rtx x;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  enum rtx_code code = GET_CODE (x);
+
+  return (code == IOR || code == XOR);
+}
+
 /* Recognize valid operators for bit instructions.  */
 
 int
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index 0c40814..b1b57f3 100644
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -1292,6 +1292,7 @@ struct cum_arg
   {"bit_operator", {XOR, AND, IOR}},					\
   {"nshift_operator", {ASHIFTRT, LSHIFTRT, ASHIFT}},			\
   {"eqne_operator", {EQ, NE}},						\
-  {"gtuleu_operator", {GTU, LEU}},
+  {"gtuleu_operator", {GTU, LEU}},					\
+  {"iorxor_operator", {IOR, XOR}},
 
 #endif /* ! GCC_H8300_H */
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 495fba3..61ae4b6 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -2765,17 +2765,42 @@
   [(set_attr "cc" "clobber")
    (set_attr "length" "6")])
 
-;; ior:HI
+;; [ix]or:HI
 
-(define_insn "*iorhi3_zext"
+(define_insn "*ixorhi3_zext"
   [(set (match_operand:HI 0 "register_operand" "=r")
-	(ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
-		(match_operand:HI 2 "register_operand" "0")))]
+	(match_operator:HI 1 "iorxor_operator"
+	  [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
+	   (match_operand:HI 3 "register_operand" "0")]))]
+  ""
+  "%c1.b\\t%X2,%s0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+;; [ix]or:SI
+
+(define_insn "*ixorsi3_zext_qi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(match_operator:SI 1 "iorxor_operator"
+	  [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
+	   (match_operand:SI 3 "register_operand" "0")]))]
+  ""
+  "%c1.b\\t%X2,%w0"
+  [(set_attr "cc" "clobber")
+   (set_attr "length" "2")])
+
+(define_insn "*ixorsi3_zext_hi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(match_operator:SI 1 "iorxor_operator"
+	  [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
+	   (match_operand:SI 3 "register_operand" "0")]))]
   ""
-  "or\\t%X1,%s0"
+  "%c1.w\\t%T2,%f0"
   [(set_attr "cc" "clobber")
    (set_attr "length" "2")])
 
+;; ior:HI
+
 (define_insn "*iorhi3_ashift_8"
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
@@ -2808,24 +2833,6 @@
 
 ;; ior:SI
 
-(define_insn "*iorsi3_zexthi"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
-		(match_operand:SI 2 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "or.w\\t%T1,%f0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "2")])
-
-(define_insn "*iorsi3_zextqi"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
-		(match_operand:SI 2 "register_operand" "0")))]
-  ""
-  "or\\t%X1,%w0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "2")])
-
 (define_insn "*iorsi3_ashift_16"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
@@ -3033,37 +3040,6 @@
 		 (match_dup 0)))]
   "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
 
-;; xor:HI
-
-(define_insn "*xorhi3_zextqi"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(xor:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
-		(match_operand:HI 2 "register_operand" "0")))]
-  ""
-  "xor\\t%X1,%s0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "2")])
-
-;; xor:SI
-
-(define_insn "*xorsi3_zexthi"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(xor:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
-		(match_operand:SI 2 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "xor.w\\t%T1,%f0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "2")])
-
-(define_insn "*xorsi3_zextqi"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(xor:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
-		(match_operand:SI 2 "register_operand" "0")))]
-  ""
-  "xor\\t%X1,%w0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "2")])
-
 ;; ashift:SI
 
 (define_insn_and_split "*ashiftsi_sextqi_7"