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| author | Maxim Kuvyrkov <maxim@codesourcery.com> | 2012-08-16 02:13:21 +0000 |
|---|---|---|
| committer | Sandra Loosemore <sandra@gcc.gnu.org> | 2012-08-15 22:13:21 -0400 |
| commit | a9d2a88c55390736d1e948c0032e4aa79df59eda (patch) | |
| tree | 962adf21328b8510b3b21f4eaf1dd8032d80b80f | |
| parent | 18efc0dd75dd55353f0b93f129128695289a10cd (diff) | |
| download | gcc-a9d2a88c55390736d1e948c0032e4aa79df59eda.zip gcc-a9d2a88c55390736d1e948c0032e4aa79df59eda.tar.gz gcc-a9d2a88c55390736d1e948c0032e4aa79df59eda.tar.bz2 | |
Add missing ChangeLog entry for r190406
From-SVN: r190436
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/mips/mips-dspr2.md | 31 |
2 files changed, 38 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 52e4deea..9cdba85 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -306,6 +306,13 @@ (neon_vdup_n<mode> VX, V32): Likewise. (neon_vdup_nv2di): Likewise. +2012-08-14 Maxim Kuvyrkov <maxim@codesourcery.com> + + * config/mips/mips.md (define_attr accum_in): New instruction + attribute. Set it for imadd and fmadd patterns. + * config/mips/mips.c (mips_linked_madd_p): Use accum_in to extract + accumulator register. + 2012-08-14 Diego Novillo <dnovillo@google.com> Merge from cxx-conversion branch. Configury. diff --git a/gcc/config/mips/mips-dspr2.md b/gcc/config/mips/mips-dspr2.md index 0d02580..248e46e 100644 --- a/gcc/config/mips/mips-dspr2.md +++ b/gcc/config/mips/mips-dspr2.md @@ -68,6 +68,7 @@ UNSPEC_DPAQX_SA_W_PH UNSPEC_DPSQX_S_W_PH UNSPEC_DPSQX_SA_W_PH + UNSPEC_ACC_INIT ]) (define_insn "mips_absq_s_qb" @@ -630,3 +631,33 @@ [(set_attr "type" "dspmacsat") (set_attr "accum_in" "1") (set_attr "mode" "SI")]) + +;; Convert mtlo $ac[1-3],$0 => mult $ac[1-3],$0,$0 +;; mthi $ac[1-3],$0 +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (const_int 0)) + (set (match_operand:SI 1 "register_operand" "") + (const_int 0))] + "ISA_HAS_DSPR2 + && !TARGET_MIPS16 + && !TARGET_64BIT + && true_regnum (operands[0]) >= DSP_ACC_REG_FIRST + && true_regnum (operands[0]) <= DSP_ACC_REG_LAST + && true_regnum (operands[0]) / 2 == true_regnum (operands[1]) / 2" + [(parallel [(set (match_dup 0) (const_int 0)) + (set (match_dup 1) (const_int 0)) + (unspec [(const_int 0)] UNSPEC_ACC_INIT)])] +) + +(define_insn "*mips_acc_init" + [(parallel + [(set (match_operand:SI 0 "register_operand" "=a") (const_int 0)) + (set (match_operand:SI 1 "register_operand" "=a") (const_int 0)) + (unspec [(const_int 0)] UNSPEC_ACC_INIT)])] + "ISA_HAS_DSPR2 + && !TARGET_MIPS16 + && !TARGET_64BIT" + "mult\t%q0,$0,$0\t\t# Clear ACC HI/LO" + [(set_attr "type" "imul") + (set_attr "mode" "SI")]) |