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| author | Jerry Zhang Jian <jerry.zhangjian@sifive.com> | 2025-04-30 15:34:07 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2025-04-30 17:26:24 +0800 |
| commit | a992164c2899735525a7a267654473b7e527ef0d (patch) | |
| tree | 7716c1ef74e61c9e054dcd20753a612e698c62f6 | |
| parent | 83bb288faa39a0bf5ce2d62e21a090a130d8dda4 (diff) | |
| download | gcc-a992164c2899735525a7a267654473b7e527ef0d.zip gcc-a992164c2899735525a7a267654473b7e527ef0d.tar.gz gcc-a992164c2899735525a7a267654473b7e527ef0d.tar.bz2 | |
RISC-V: Fix missing implied Zicsr from Zve32x
The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-19.c: set the march to rv64im_zve32x
instead of rv64gc_zve32x to avoid Zicsr implied by g. Extra m is
added to avoid current 'V' extension requires 'M' extension
Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
| -rw-r--r-- | gcc/common/config/riscv/riscv-common.cc | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/predef-19.c | 34 |
2 files changed, 8 insertions, 27 deletions
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 15df22d..145a0f2 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -137,6 +137,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zve64f", "f"}, {"zve64d", "d"}, + {"zve32x", "zicsr"}, {"zve32x", "zvl32b"}, {"zve32f", "zve32x"}, {"zve32f", "zvl32b"}, diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c b/gcc/testsuite/gcc.target/riscv/predef-19.c index 2b90702..ca3d57a 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-19.c +++ b/gcc/testsuite/gcc.target/riscv/predef-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=rv64gc_zve32x -mabi=lp64d -mcmodel=medlow -misa-spec=2.2" } */ +/* { dg-options "-O2 -march=rv64im_zve32x -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ int main () { @@ -15,50 +15,30 @@ int main () { #error "__riscv_i" #endif -#if !defined(__riscv_c) -#error "__riscv_c" -#endif - #if defined(__riscv_e) #error "__riscv_e" #endif -#if !defined(__riscv_a) -#error "__riscv_a" -#endif - #if !defined(__riscv_m) #error "__riscv_m" #endif -#if !defined(__riscv_f) -#error "__riscv_f" -#endif - -#if !defined(__riscv_d) -#error "__riscv_d" -#endif - -#if defined(__riscv_v) -#error "__riscv_v" +#if !defined(__riscv_zicsr) +#error "__riscv_zicsr" #endif -#if defined(__riscv_zvl128b) -#error "__riscv_zvl128b" +#if !defined(_riscv_zmmul) +#error "__riscv_zmmul" #endif -#if defined(__riscv_zvl64b) -#error "__riscv_zvl64b" +#if !defined(__riscv_zve32x) +#error "__riscv_zve32x" #endif #if !defined(__riscv_zvl32b) #error "__riscv_zvl32b" #endif -#if !defined(__riscv_zve32x) -#error "__riscv_zve32x" -#endif - #if !defined(__riscv_vector) #error "__riscv_vector" #endif |