[arm] Add initial support for Arm Cortex-M55

This patch adds initial -mcpu support for the Arm Cortex-M55 CPU.
This CPU is an Armv8.1-M Mainline CPU supporting MVE.
An option to disable floating-point (and MVE) is provided with the +nofp.
For GCC 11 I'd like to add further fine-grained options to enable integer-only MVE
but that needs a bit more elaborate surgery in arm-cpus.in that I don't want to do
in GCC 10 at this stage.

As this CPU is not supported in gas and I don't want to couple GCC 10 to the very
latest binutils anyway, this CPU emits the cpu string in the assembly file as a build attribute
rather than a .cpu directive, thus sparing us the need to support .cpu cortex-m55 in gas.
The .cpu directive in gas isn't used for anything besides setting the Tag_CPU_name
build attribute anyway (which itself is not used by any tools I'm aware of).
All the architecture information used for target detection is already emitted using .arch_extension
directives and similar.

Bootstrapped and tested on arm-none-linux-gnueabihf. Also tested on arm-none-eabi.

2020-04-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
            Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>

	* config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
	* config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
	(ALL_QUIRKS): Add quirk_no_asmcpu.
	(cortex-m55): Define new cpu.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Likewise.
	* doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.

6 files changed, 37 insertions, 5 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5cdd4f4..85f6f4c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2020-04-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+            Andre Vieira  <andre.simoesdiasvieira@arm.com>
+            Mihail Ionescu  <mihail.ionescu@arm.com>
+
+	* config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
+	* config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
+	(ALL_QUIRKS): Add quirk_no_asmcpu.
+	(cortex-m55): Define new cpu.
+	* config/arm/arm-tables.opt: Regenerate.
+	* config/arm/arm-tune.md: Likewise.
+	* doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
+
 2020-04-22  Richard Sandiford  <richard.sandiford@arm.com>
 
 	PR tree-optimization/94700
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index fba34e5..64b8ba7 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -190,6 +190,9 @@ define feature quirk_armv6kz
 # Cortex-M3 LDRD quirk.
 define feature quirk_cm3_ldrd
 
+# Don't use .cpu assembly directive
+define feature quirk_no_asmcpu
+
 # (Very) slow multiply operations.  Should probably be a tuning bit.
 define feature smallmul
 
@@ -311,7 +314,7 @@ define fgroup DOTPROD	NEON dotprod
 # architectures.
 # xscale isn't really a 'quirk', but it isn't an architecture either and we
 # need to ignore it for matching purposes.
-define fgroup ALL_QUIRKS   quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd xscale
+define fgroup ALL_QUIRKS   quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd xscale quirk_no_asmcpu
 
 # Architecture entries
 # format:
@@ -1501,6 +1504,16 @@ begin cpu cortex-m35p
  costs v7m
 end cpu cortex-m35p
 
+begin cpu cortex-m55
+ cname cortexm55
+ tune flags LDSCHED
+ architecture armv8.1-m.main+mve.fp+fp.dp
+ isa quirk_no_asmcpu
+ option nofp remove ALL_FP MVE_FP
+ costs v7m
+ vendor 41
+end cpu cortex-m55
+
 # V8 R-profile implementations.
 begin cpu cortex-r52
  cname cortexr52
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index a51a131..ce35661 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -259,6 +259,9 @@ EnumValue
 Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p)
 
 EnumValue
+Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55)
+
+EnumValue
 Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
 
 Enum
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index b929e44..8ea9435 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -47,5 +47,5 @@
 	cortexa76,cortexa76ae,cortexa77,
 	neoversen1,cortexa75cortexa55,cortexa76cortexa55,
 	cortexm23,cortexm33,cortexm35p,
-	cortexr52"
+	cortexm55,cortexr52"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index c38776f..0151bda 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -27889,7 +27889,11 @@ arm_file_start (void)
 	{
 	  const char* truncated_name
 	    = arm_rewrite_selected_cpu (arm_active_target.core_name);
-	  asm_fprintf (asm_out_file, "\t.cpu %s\n", truncated_name);
+	  if (bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_no_asmcpu))
+	    asm_fprintf (asm_out_file, "\t.eabi_attribute 5, \"%s\"\n",
+			 truncated_name);
+	  else
+	    asm_fprintf (asm_out_file, "\t.cpu %s\n", truncated_name);
 	}
 
       if (print_tune_info)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d474882..e2bc255 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -18773,7 +18773,7 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
 @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52},
 @samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
 @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
-@samp{cortex-m35p},
+@samp{cortex-m35p}, @samp{cortex-m55},
 @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
 @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
 @samp{neoverse-n1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2},
@@ -18850,7 +18850,7 @@ Disables the floating-point and SIMD instructions on
 @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
 @samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a15.cortex-a7},
 @samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35},
-@samp{cortex-a53} and @samp{cortex-a55}.
+@samp{cortex-a53},@samp{cortex-a55} and @samp{cortex-m55}.
 
 @item +nofp.dp
 Disables the double-precision component of the floating-point instructions