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author | Richard Sandiford <rdsandiford@googlemail.com> | 2012-10-02 19:34:49 +0000 |
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committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2012-10-02 19:34:49 +0000 |
commit | a2c19e9343706412d3320e3b6b2688d01ace96a5 (patch) | |
tree | 431668293bd4a0018f9e8856e4c146862a0c276d | |
parent | c9d74da68c27d7af5c5c2edef7f723190ab461d2 (diff) | |
download | gcc-a2c19e9343706412d3320e3b6b2688d01ace96a5.zip gcc-a2c19e9343706412d3320e3b6b2688d01ace96a5.tar.gz gcc-a2c19e9343706412d3320e3b6b2688d01ace96a5.tar.bz2 |
ira-int.h (target_ira_int): Add x_ira_useful_class_mode_regs.
gcc/
* ira-int.h (target_ira_int): Add x_ira_useful_class_mode_regs.
(ira_useful_class_mode_regs): New macro.
* ira.c (clarify_prohibited_class_mode_regs): Set up
ira_useful_class_mode_regs.
* ira-color.c (setup_profitable_hard_regs): Use it to initialise
profitable_hard_regs.
From-SVN: r191996
-rw-r--r-- | gcc/ChangeLog | 9 | ||||
-rw-r--r-- | gcc/ira-color.c | 5 | ||||
-rw-r--r-- | gcc/ira-int.h | 16 | ||||
-rw-r--r-- | gcc/ira.c | 45 |
4 files changed, 53 insertions, 22 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ad6c14b..2bdf661 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,14 @@ 2012-10-02 Richard Sandiford <rdsandiford@googlemail.com> + * ira-int.h (target_ira_int): Add x_ira_useful_class_mode_regs. + (ira_useful_class_mode_regs): New macro. + * ira.c (clarify_prohibited_class_mode_regs): Set up + ira_useful_class_mode_regs. + * ira-color.c (setup_profitable_hard_regs): Use it to initialise + profitable_hard_regs. + +2012-10-02 Richard Sandiford <rdsandiford@googlemail.com> + * ira.h (target_ira): Add x_ira_class_singleton. (ira_class_singleton): New macro. * ira.c (setup_prohibited_class_mode_regs): Set up ira_class_singleton. diff --git a/gcc/ira-color.c b/gcc/ira-color.c index ea933be..fc2e4e8 100644 --- a/gcc/ira-color.c +++ b/gcc/ira-color.c @@ -1023,10 +1023,9 @@ setup_profitable_hard_regs (void) CLEAR_HARD_REG_SET (data->profitable_hard_regs); else { + mode = ALLOCNO_MODE (a); COPY_HARD_REG_SET (data->profitable_hard_regs, - reg_class_contents[aclass]); - AND_COMPL_HARD_REG_SET (data->profitable_hard_regs, - ira_no_alloc_regs); + ira_useful_class_mode_regs[aclass][mode]); nobj = ALLOCNO_NUM_OBJECTS (a); for (k = 0; k < nobj; k++) { diff --git a/gcc/ira-int.h b/gcc/ira-int.h index 8d44e35..bde6986 100644 --- a/gcc/ira-int.h +++ b/gcc/ira-int.h @@ -816,6 +816,20 @@ struct target_ira_int { values for given mode are zero. */ HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES]; + /* Index [CL][M] contains R if R appears somewhere in a register of the form: + + (reg:M R'), R' not in x_ira_prohibited_class_mode_regs[CL][M] + + For example, if: + + - (reg:M 2) is valid and occupies two registers; + - register 2 belongs to CL; and + - register 3 belongs to the same pressure class as CL + + then (reg:M 2) contributes to [CL][M] and registers 2 and 3 will be + in the set. */ + HARD_REG_SET x_ira_useful_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES]; + /* The value is number of elements in the subsequent array. */ int x_ira_important_classes_num; @@ -902,6 +916,8 @@ extern struct target_ira_int *this_target_ira_int; (this_target_ira_int->x_ira_class_hard_reg_index) #define ira_prohibited_class_mode_regs \ (this_target_ira_int->x_ira_prohibited_class_mode_regs) +#define ira_useful_class_mode_regs \ + (this_target_ira_int->x_ira_useful_class_mode_regs) #define ira_important_classes_num \ (this_target_ira_int->x_ira_important_classes_num) #define ira_important_classes \ @@ -1495,29 +1495,36 @@ clarify_prohibited_class_mode_regs (void) for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) for (j = 0; j < NUM_MACHINE_MODES; j++) - for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) - { - hard_regno = ira_class_hard_regs[cl][k]; - if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno)) - continue; - nregs = hard_regno_nregs[hard_regno][j]; - if (hard_regno + nregs > FIRST_PSEUDO_REGISTER) - { - SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], - hard_regno); - continue; - } - pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; - for (nregs-- ;nregs >= 0; nregs--) - if (((enum reg_class) pclass - != ira_pressure_class_translate[REGNO_REG_CLASS - (hard_regno + nregs)])) + { + CLEAR_HARD_REG_SET (ira_useful_class_mode_regs[cl][j]); + for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) + { + hard_regno = ira_class_hard_regs[cl][k]; + if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno)) + continue; + nregs = hard_regno_nregs[hard_regno][j]; + if (hard_regno + nregs > FIRST_PSEUDO_REGISTER) { SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno); - break; + continue; } - } + pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; + for (nregs-- ;nregs >= 0; nregs--) + if (((enum reg_class) pclass + != ira_pressure_class_translate[REGNO_REG_CLASS + (hard_regno + nregs)])) + { + SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], + hard_regno); + break; + } + if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], + hard_regno)) + add_to_hard_reg_set (&ira_useful_class_mode_regs[cl][j], + (enum machine_mode) j, hard_regno); + } + } } /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST |