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| author | Wolfgang Gellerich <gellerich@de,ibm.com> | 2009-01-30 10:50:31 +0000 |
|---|---|---|
| committer | Andreas Krebbel <krebbel@gcc.gnu.org> | 2009-01-30 10:50:31 +0000 |
| commit | 9fec758df2bc78c0babf774ae98ee0c3146501f1 (patch) | |
| tree | 419d069125d380d724526d64793b64370d1caf46 | |
| parent | 9e8be1e49e810a2147662a085f5b2e62d79c06b9 (diff) | |
| download | gcc-9fec758df2bc78c0babf774ae98ee0c3146501f1.zip gcc-9fec758df2bc78c0babf774ae98ee0c3146501f1.tar.gz gcc-9fec758df2bc78c0babf774ae98ee0c3146501f1.tar.bz2 | |
2009-01-30 Wolfgang Gellerich <gellerich@de,ibm.com>
* config/s390/s390.md (*insv<mode>_reg_extimm): Removed.
(*insv_h_di_reg_extimm): New insn.
(*insv_l<mode>_reg_extimm): New insn.
From-SVN: r143786
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/s390/s390.md | 29 |
2 files changed, 23 insertions, 16 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6dc807b..c700951 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,10 +1,16 @@ -Hariharan Sandanagobalane <hariharan@picochip.com> +2009-01-30 Wolfgang Gellerich <gellerich@de,ibm.com> + + * config/s390/s390.md (*insv<mode>_reg_extimm): Removed. + (*insv_h_di_reg_extimm): New insn. + (*insv_l<mode>_reg_extimm): New insn. + +2009-01-30 Hariharan Sandanagobalane <hariharan@picochip.com> * config/picochip/picochip.c (flag_conserve_stack): set PARAM_LARGE_STACK_FRAME and PARAM_STACK_FRAME_GROWTH to zero under fconserve-stack. Reduce call-overhead used by inliner. -Hariharan Sandanagobalane <hariharan@picochip.com> +2009-01-30 Hariharan Sandanagobalane <hariharan@picochip.com> PR/38157 * common.opt (flag_conserve_stack): Initialised to zero. diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 9c21977..0e5546a 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -3378,27 +3378,28 @@ [(set_attr "op_type" "RI") (set_attr "z10prop" "z10_super_E1")]) +; Update the left-most 32 bit of a DI. +(define_insn "*insv_h_di_reg_extimm" + [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") + (const_int 32) + (const_int 0)) + (match_operand:DI 1 "const_int_operand" "n"))] + "TARGET_EXTIMM" + "iihf\t%0,%o1" + [(set_attr "op_type" "RIL") + (set_attr "z10prop" "z10_fwd_E1")]) -(define_insn "*insv<mode>_reg_extimm" +; Update the right-most 32 bit of a DI, or the whole of a SI. +(define_insn "*insv_l<mode>_reg_extimm" [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") (const_int 32) (match_operand 1 "const_int_operand" "n")) (match_operand:P 2 "const_int_operand" "n"))] "TARGET_EXTIMM - && INTVAL (operands[1]) >= 0 - && INTVAL (operands[1]) < BITS_PER_WORD - && INTVAL (operands[1]) % 32 == 0" -{ - switch (BITS_PER_WORD - INTVAL (operands[1])) - { - case 64: return "iihf\t%0,%o2"; break; - case 32: return "iilf\t%0,%o2"; break; - default: gcc_unreachable(); - } -} + && BITS_PER_WORD - INTVAL (operands[1]) == 32" + "iilf\t%0,%o2" [(set_attr "op_type" "RIL") - (set_attr "z10prop" "z10_fwd_E1")]) - + (set_attr "z10prop" "z10_fwd_A1")]) ; ; extendsidi2 instruction pattern(s). |