RISC-V: Support --target-help for -mcpu/-mtune

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc (riscv_tunes): New.
	(riscv_get_valid_option_values): New.
	(TARGET_GET_VALID_OPTION_VALUES): New.
	* config/riscv/riscv-cores.def (RISCV_TUNE): New, define options
	for tune here.
	(RISCV_CORE): Fix comment.
	* config/riscv/riscv.cc (riscv_tune_info_table): Move definition to
	riscv-cores.def.

3 files changed, 80 insertions, 10 deletions

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index c39ed2e..697bfe4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -224,6 +224,14 @@ static const riscv_cpu_info riscv_cpu_tables[] =
     {NULL, NULL, NULL}
 };
 
+static const char *riscv_tunes[] =
+{
+#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) \
+    TUNE_NAME,
+#include "../../../config/riscv/riscv-cores.def"
+    NULL
+};
+
 static const char *riscv_supported_std_ext (void);
 
 static riscv_subset_list *current_subset_list = NULL;
@@ -1683,6 +1691,41 @@ riscv_compute_multilib (
     return xstrdup (multilib_infos[best_match_multi_lib].path.c_str ());
 }
 
+vec<const char *>
+riscv_get_valid_option_values (int option_code,
+			       const char *prefix ATTRIBUTE_UNUSED)
+{
+  vec<const char *> v;
+  v.create (0);
+  opt_code opt = (opt_code) option_code;
+
+  switch (opt)
+    {
+    case OPT_mtune_:
+      {
+	const char **tune = &riscv_tunes[0];
+	for (;*tune; ++tune)
+	  v.safe_push (*tune);
+
+	const riscv_cpu_info *cpu_info = &riscv_cpu_tables[0];
+	for (;cpu_info->name; ++cpu_info)
+	  v.safe_push (cpu_info->name);
+      }
+      break;
+    case OPT_mcpu_:
+      {
+	const riscv_cpu_info *cpu_info = &riscv_cpu_tables[0];
+	for (;cpu_info->name; ++cpu_info)
+	  v.safe_push (cpu_info->name);
+      }
+      break;
+    default:
+      break;
+    }
+
+  return v;
+}
+
 #undef TARGET_COMPUTE_MULTILIB
 #define TARGET_COMPUTE_MULTILIB riscv_compute_multilib
 #endif
@@ -1701,4 +1744,7 @@ static const struct default_options riscv_option_optimization_table[] =
 #undef TARGET_HANDLE_OPTION
 #define TARGET_HANDLE_OPTION riscv_handle_option
 
+#undef  TARGET_GET_VALID_OPTION_VALUES
+#define TARGET_GET_VALID_OPTION_VALUES riscv_get_valid_option_values
+
 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index ecb5e21..b84ad99 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -17,19 +17,46 @@
    along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
+/* This is a list of tune that implement RISC-V.
+
+   Before using #include to read this file, define a macro:
+
+      RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)
+
+   The TUNE_NAME is the name of the micro-arch, represented as a string.
+   The PIPELINE_MODEL is the pipeline model of the micro-arch, represented as a
+   string, defined in riscv.md.
+   The TUNE_INFO is the detail cost model for this core, represented as an
+   identifier, reference to riscv.cc.  */
+
+#ifndef RISCV_TUNE
+#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)
+#endif
+
+RISCV_TUNE("rocket", generic, rocket_tune_info)
+RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
+RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
+RISCV_TUNE("sifive-7-series", generic, sifive_7_tune_info)
+RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("size", generic, optimize_size_tune_info)
+
+#undef RISCV_TUNE
+
 /* This is a list of cores that implement RISC-V.
 
    Before using #include to read this file, define a macro:
 
-      RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO)
+      RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH)
 
    The CORE_NAME is the name of the core, represented as a string.
    The ARCH is the default arch of the core, represented as a string,
    can be NULL if no default arch.
    The MICRO_ARCH is the name of the core for which scheduling decisions
-   will be made, represented as an identifier.
-   The TUNE_INFO is the detail cost model for this core, represented as an
-   identifier, reference to riscv-tunes.def.  */
+   will be made, represented as an identifier.  */
+
+#ifndef RISCV_CORE
+#define RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH)
+#endif
 
 RISCV_CORE("sifive-e20",      "rv32imc",    "rocket")
 RISCV_CORE("sifive-e21",      "rv32imac",   "rocket")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 53a91a1..4e18a43 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -396,12 +396,9 @@ static const unsigned gpr_save_reg_order[] = {
 
 /* A table describing all the processors GCC knows about.  */
 static const struct riscv_tune_info riscv_tune_info_table[] = {
-  { "rocket", generic, &rocket_tune_info },
-  { "sifive-3-series", generic, &rocket_tune_info },
-  { "sifive-5-series", generic, &rocket_tune_info },
-  { "sifive-7-series", sifive_7, &sifive_7_tune_info },
-  { "thead-c906", generic, &thead_c906_tune_info },
-  { "size", generic, &optimize_size_tune_info },
+#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)	\
+  { TUNE_NAME, PIPELINE_MODEL, & TUNE_INFO},
+#include "riscv-cores.def"
 };
 
 void riscv_frame_info::reset(void)