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| author | Andrew Stubbs <ams@codesourcery.com> | 2020-05-18 14:05:02 +0100 |
|---|---|---|
| committer | Andrew Stubbs <ams@codesourcery.com> | 2020-05-29 12:17:06 +0100 |
| commit | 961c2aac7fd1050e1dc1c11f78c10579c7d24164 (patch) | |
| tree | ad5febe862b5eeca3662f44605b6731a03fb8052 | |
| parent | 7688e5e8c4d46102a0cc0b9c25191ac7dde0d285 (diff) | |
| download | gcc-961c2aac7fd1050e1dc1c11f78c10579c7d24164.zip gcc-961c2aac7fd1050e1dc1c11f78c10579c7d24164.tar.gz gcc-961c2aac7fd1050e1dc1c11f78c10579c7d24164.tar.bz2 | |
amdgcn: Fix VCC early clobber
gcc/ChangeLog:
2020-05-28 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-valu.md (add<mode>3_vcc_zext_dup): Add early clobber.
(add<mode>3_vcc_zext_dup_exec): Likewise.
(add<mode>3_vcc_zext_dup2): Likewise.
(add<mode>3_vcc_zext_dup2_exec): Likewise.
| -rw-r--r-- | gcc/config/gcn/gcn-valu.md | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index d31fe50..6d7feca 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -1380,13 +1380,13 @@ (set_attr "length" "8")]) (define_insn_and_split "add<mode>3_vcc_zext_dup" - [(set (match_operand:V_DI 0 "register_operand" "= v, v") + [(set (match_operand:V_DI 0 "register_operand" "= v, v") (plus:V_DI (zero_extend:V_DI (vec_duplicate:<VnSI> - (match_operand:SI 1 "gcn_alu_operand" " BSv, ASv"))) - (match_operand:V_DI 2 "gcn_alu_operand" " vDA, vDb"))) - (set (match_operand:DI 3 "register_operand" "=SgcV,SgcV") + (match_operand:SI 1 "gcn_alu_operand" " BSv, ASv"))) + (match_operand:V_DI 2 "gcn_alu_operand" " vDA, vDb"))) + (set (match_operand:DI 3 "register_operand" "=&SgcV,&SgcV") (ltu:DI (plus:V_DI (zero_extend:V_DI (vec_duplicate:<VnSI> (match_dup 1))) (match_dup 2)) @@ -1424,16 +1424,16 @@ }) (define_insn_and_split "add<mode>3_vcc_zext_dup_exec" - [(set (match_operand:V_DI 0 "register_operand" "= v, v") + [(set (match_operand:V_DI 0 "register_operand" "= v, v") (vec_merge:V_DI (plus:V_DI (zero_extend:V_DI (vec_duplicate:<VnSI> - (match_operand:SI 1 "gcn_alu_operand" " ASv, BSv"))) - (match_operand:V_DI 2 "gcn_alu_operand" " vDb, vDA")) - (match_operand:V_DI 4 "gcn_register_or_unspec_operand" " U0, U0") - (match_operand:DI 5 "gcn_exec_reg_operand" " e, e"))) - (set (match_operand:DI 3 "register_operand" "=SgcV,SgcV") + (match_operand:SI 1 "gcn_alu_operand" " ASv, BSv"))) + (match_operand:V_DI 2 "gcn_alu_operand" " vDb, vDA")) + (match_operand:V_DI 4 "gcn_register_or_unspec_operand" " U0, U0") + (match_operand:DI 5 "gcn_exec_reg_operand" " e, e"))) + (set (match_operand:DI 3 "register_operand" "=&SgcV,&SgcV") (and:DI (ltu:DI (plus:V_DI (zero_extend:V_DI (vec_duplicate:<VnSI> (match_dup 1))) @@ -1481,11 +1481,11 @@ }) (define_insn_and_split "add<mode>3_vcc_zext_dup2" - [(set (match_operand:V_DI 0 "register_operand" "= v") + [(set (match_operand:V_DI 0 "register_operand" "= v") (plus:V_DI (zero_extend:V_DI (match_operand:<VnSI> 1 "gcn_alu_operand" " vA")) (vec_duplicate:V_DI (match_operand:DI 2 "gcn_alu_operand" " DbSv")))) - (set (match_operand:DI 3 "register_operand" "=SgcV") + (set (match_operand:DI 3 "register_operand" "=&SgcV") (ltu:DI (plus:V_DI (zero_extend:V_DI (match_dup 1)) (vec_duplicate:V_DI (match_dup 2))) @@ -1523,14 +1523,14 @@ }) (define_insn_and_split "add<mode>3_vcc_zext_dup2_exec" - [(set (match_operand:V_DI 0 "register_operand" "= v") + [(set (match_operand:V_DI 0 "register_operand" "= v") (vec_merge:V_DI (plus:V_DI (zero_extend:V_DI (match_operand:<VnSI> 1 "gcn_alu_operand" "vA")) (vec_duplicate:V_DI (match_operand:DI 2 "gcn_alu_operand" "BSv"))) - (match_operand:V_DI 4 "gcn_register_or_unspec_operand" " U0") - (match_operand:DI 5 "gcn_exec_reg_operand" " e"))) - (set (match_operand:DI 3 "register_operand" "=SgcV") + (match_operand:V_DI 4 "gcn_register_or_unspec_operand" " U0") + (match_operand:DI 5 "gcn_exec_reg_operand" " e"))) + (set (match_operand:DI 3 "register_operand" "=&SgcV") (and:DI (ltu:DI (plus:V_DI (zero_extend:V_DI (match_dup 1)) |