alpha.h (enum reg_class): Add PV_REG.

        * config/alpha/alpha.h (enum reg_class): Add PV_REG.
        (REG_CLASS_NAMES, REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
        (REG_CLASS_FROM_LETTER): Assign it to 'c'.
        * config/alpha/alpha.md (call_osf_1): Use it.
        (call_value_osf_1): Likewise.

From-SVN: r37091

3 files changed, 16 insertions, 8 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 39e1ff3..db875db 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,11 @@
 2000-10-27  Richard Henderson  <rth@redhat.com>
 
+	* config/alpha/alpha.h (enum reg_class): Add PV_REG.
+	(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
+	(REG_CLASS_FROM_LETTER): Assign it to 'c'.
+	* config/alpha/alpha.md (call_osf_1): Use it.
+	(call_value_osf_1): Likewise.
+
 	* config/ia64/ia64.c: Revert 10-23 patch.
 	(ia64_hard_regno_rename_ok): New.
 	* config/ia64/ia64-protos.h: Declare it.
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index 4d5729e..428bd47 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -719,7 +719,7 @@ extern const char *alpha_mlat_string;	/* For -mmemory-latency= */
    For any two classes, it is very desirable that there be another
    class that represents their union.  */
    
-enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
+enum reg_class { NO_REGS, PV_REG, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
 		 LIM_REG_CLASSES };
 
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
@@ -727,22 +727,24 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
 /* Give names of register classes as strings for dump file.   */
 
 #define REG_CLASS_NAMES				\
- {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
+ {"NO_REGS", "PV_REG", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
 
 /* Define which registers fit in which classes.
    This is an initializer for a vector of HARD_REG_SET
    of length N_REG_CLASSES.  */
 
 #define REG_CLASS_CONTENTS	\
-  { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
+  { {0, 0}, {0x08000000, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
 
 /* The same information, inverted:
    Return the class number of the smallest class containing
    reg number REGNO.  This could be a conditional expression
    or could index an array.  */
 
-#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
+#define REGNO_REG_CLASS(REGNO)			\
+ ((REGNO) == 27 ? PV_REG			\
+  : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS	\
+  : GENERAL_REGS)
 
 /* The class value for index registers, and the one for base regs.  */
 #define INDEX_REG_CLASS NO_REGS
@@ -751,7 +753,7 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
 /* Get reg_class from a letter such as appears in the machine description.  */
 
 #define REG_CLASS_FROM_LETTER(C)	\
- ((C) == 'f' ? FLOAT_REGS : NO_REGS)
+ ((C) == 'c' ? PV_REG : (C) == 'f' ? FLOAT_REGS : NO_REGS)
 
 /* Define this macro to change register usage conditional on target flags.  */
 /* #define CONDITIONAL_REGISTER_USAGE  */
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 4fcaaec..eb1c2e5 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -4223,7 +4223,7 @@
 }")
 
 (define_insn "*call_osf_1"
-  [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
+  [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
 	 (match_operand 1 "" ""))
    (clobber (reg:DI 27))
    (clobber (reg:DI 26))]
@@ -5976,7 +5976,7 @@
 
 (define_insn "*call_value_osf_1"
   [(set (match_operand 0 "" "")
-	(call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
+	(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,i"))
 	      (match_operand 2 "" "")))
    (clobber (reg:DI 27))
    (clobber (reg:DI 26))]