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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:17:25 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:17:25 -0700 |
| commit | 9377b54a62a4b6424194c3f9d755eb0f84fce726 (patch) | |
| tree | eb22f59f2ea152d6d77cee1feae09844d0b8ff93 | |
| parent | 73371f6a702f497479ce50bf81695a5721532307 (diff) | |
| download | gcc-9377b54a62a4b6424194c3f9d755eb0f84fce726.zip gcc-9377b54a62a4b6424194c3f9d755eb0f84fce726.tar.gz gcc-9377b54a62a4b6424194c3f9d755eb0f84fce726.tar.bz2 | |
i386: Emulate MMX mmx_umulv4hi3_highpart with SSE
Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check
TARGET_MMX and TARGET_MMX_WITH_SSE.
(*mmx_umulv4hi3_highpart): Add SSE emulation.
From-SVN: r271233
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 26 |
2 files changed, 23 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3c003fc..e46067f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,13 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check + TARGET_MMX and TARGET_MMX_WITH_SSE. + (*mmx_umulv4hi3_highpart): Add SSE emulation. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (mmx_pmovmskb): Changed to define_insn_and_split to support SSE emulation. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index cb6da2d..e2a1f4c 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -806,28 +806,34 @@ (lshiftrt:V4SI (mult:V4SI (zero_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand")) + (match_operand:V4HI 1 "register_mmxmem_operand")) (zero_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand"))) + (match_operand:V4HI 2 "register_mmxmem_operand"))) (const_int 16))))] - "TARGET_SSE || TARGET_3DNOW_A" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") (define_insn "*mmx_umulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (truncate:V4HI (lshiftrt:V4SI (mult:V4SI (zero_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "%0")) + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv")) (zero_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv"))) (const_int 16))))] - "(TARGET_SSE || TARGET_3DNOW_A) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmulhuw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + "@ + pmulhuw\t{%2, %0|%0, %2} + pmulhuw\t{%2, %0|%0, %2} + vpmulhuw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,ssemul,ssemul") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_pmaddwd" [(set (match_operand:V2SI 0 "register_operand") |