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| author | Andrew Carlotti <andrew.carlotti@arm.com> | 2025-01-08 18:29:27 +0000 |
|---|---|---|
| committer | Andrew Carlotti <andrew.carlotti@arm.com> | 2025-01-24 19:01:02 +0000 |
| commit | 936463004836cb565f4fc4773dccedbfccf0028f (patch) | |
| tree | 75d6407275d64aac64ee0bbf5ee8b4c47eb99ffc | |
| parent | c4dae80357ccf2e035d8e9ec0a3bb319344c5b41 (diff) | |
| download | gcc-936463004836cb565f4fc4773dccedbfccf0028f.zip gcc-936463004836cb565f4fc4773dccedbfccf0028f.tar.gz gcc-936463004836cb565f4fc4773dccedbfccf0028f.tar.bz2 | |
aarch64: Improve mcpu/march conflict check
Features from a cpu or base architecture that were explicitly disabled
by a +nofeat option were being incorrectly added back in before checking
for conflicts between -mcpu and -march options. This patch instead
compares the returned feature masks directly.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_override_options): Compare
returned feature masks directly.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/target_attr_crypto_ice_1.c: Prune warning.
* gcc.target/aarch64/target_attr_crypto_ice_2.c: Ditto.
| -rw-r--r-- | gcc/config/aarch64/aarch64.cc | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c | 1 |
3 files changed, 4 insertions, 5 deletions
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 9c4e9bc..e7a7541 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -19289,13 +19289,10 @@ aarch64_override_options (void) cpu features would end up disabling an achitecture feature. In otherwords the cpu features need to be a strict superset of the arch features and if so prefer the -march ISA flags. */ - auto full_arch_flags = arch->flags | arch_isa; - auto full_cpu_flags = cpu->flags | cpu_isa; - if (~full_cpu_flags & full_arch_flags) + if (~cpu_isa & arch_isa) { std::string ext_diff - = aarch64_get_extension_string_for_isa_flags (full_arch_flags, - full_cpu_flags); + = aarch64_get_extension_string_for_isa_flags (arch_isa, cpu_isa); warning (0, "switch %<-mcpu=%s%> conflicts with %<-march=%s%> switch " "and resulted in options %qs being added", aarch64_cpu_string, diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c index 3b354c0..f13e5e2 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */ +/* { dg-prune-output "warning: switch .* conflicts" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c index d0a62b8..ab25492 100644 --- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mcpu=thunderx+nofp -march=armv8-a" } */ +/* { dg-prune-output "warning: switch .* conflicts" } */ /* Make sure that we don't ICE when dealing with vector parameters in a simd-tagged function within a non-simd translation unit. */ |