Support Intel AMX-TF32

gcc/ChangeLog:

	* common/config/i386/cpuinfo.h (get_available_features):
	Detect AMX-TF32.
	* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_TF32_SET,
	OPTION_MASK_ISA2_AMX_TF32_UNSET): New.
	(ix86_handle_option): Handle -mamx-tf32.
	* common/config/i386/i386-cpuinfo.h (enum processor_features):
	Add FEATURE_AMX_TF32.
	* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
	amx-tf32.
	* config.gcc: Add amxtf32intrin.h
	* config/i386/cpuid.h (bit_AMX_TF32): New.
	* config/i386/i386-c.cc (ix86_target_macros_internal): Handle amx-tf32.
	* config/i386/i386-isa.def (AMX_TF32): Add DEF_PTA(AMX_TF32).
	* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
	Handle amx-tf32.
	* config/i386/i386.opt: Add option -mamx-tf32.
	* config/i386/i386.opt.urls: Regenerated.
	* config/i386/immintrin.h: Include amxtf32intrin.h.
	* doc/extend.texi: Document amx-tf32.
	* doc/invoke.texi: Document -mamx-tf32.
	* doc/sourcebuild.texi: Document target amx-tf32.
	* config/i386/amxtf32intrin.h: New file.

gcc/testsuite/ChangeLog:

	* g++.dg/other/i386-2.C: Add -mamx-tf32.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.target/i386/amx-check.h: Add cpu check for AMX-TF32.
	* gcc.target/i386/funcspec-56.inc: Add new target attribute.
	* gcc.target/i386/sse-12.c: Add -mamx-tf32.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Add amx-tf32.
	* gcc.target/i386/sse-23.c: Ditto.
	* lib/target-supports.exp (check_effective_target_amx_tf32): New.
	* gcc.target/i386/amx-helper.h: New file for tf32 support.
	* gcc.target/i386/amxtf32-asmatt-1.c: New test.
	* gcc.target/i386/amxtf32-asmintel-1.c: Ditto.
	* gcc.target/i386/amxtf32-mmultf32ps-2.c: Ditto.

30 files changed, 217 insertions, 15 deletions

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 67724c3..5d0a644 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -1003,6 +1003,8 @@ get_available_features (struct __processor_model *cpu_model,
 	{
 	  if (eax & bit_AMX_AVX512)
 	    set_feature (FEATURE_AMX_AVX512);
+	  if (eax & bit_AMX_TF32)
+	    set_feature (FEATURE_AMX_TF32);
 	}
     }
 
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index e8e3eb1..74ad039 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -130,6 +130,8 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_AMX_AVX512_SET \
   (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AVX10_2_512_SET \
    | OPTION_MASK_ISA2_AMX_AVX512)
+#define OPTION_MASK_ISA2_AMX_TF32_SET \
+  (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_TF32)
 
 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
    as -msse4.2.  */
@@ -292,7 +294,8 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_AMX_TILE_UNSET \
   (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \
    | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \
-   | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
+   | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET | OPTION_MASK_ISA2_AMX_AVX512_UNSET \
+   | OPTION_MASK_ISA2_AMX_TF32_UNSET)
 #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
 #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
 #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
@@ -323,6 +326,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_AVX10_2_512_UNSET \
   (OPTION_MASK_ISA2_AVX10_2_512 | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
 #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
+#define OPTION_MASK_ISA2_AMX_TF32_UNSET OPTION_MASK_ISA2_AMX_TF32
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
    as -mno-sse4.1. */
@@ -1429,6 +1433,19 @@ ix86_handle_option (struct gcc_options *opts,
 	}
       return true;
 
+    case OPT_mamx_tf32:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TF32_SET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TF32_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TF32_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TF32_UNSET;
+	}
+      return true;
+
     case OPT_mfma:
       if (value)
 	{
diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index cc5bb0d..d19de25 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -270,6 +270,7 @@ enum processor_features
   FEATURE_AVX10_2_256,
   FEATURE_AVX10_2_512,
   FEATURE_AMX_AVX512,
+  FEATURE_AMX_TF32,
   CPU_FEATURE_MAX
 };
 
diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
index 7ea852a..0ba2e88 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -191,4 +191,5 @@ ISA_NAMES_TABLE_START
   ISA_NAMES_TABLE_ENTRY("avx10.2-512", FEATURE_AVX10_2_512, P_NONE, "-mavx10.2-512")
   ISA_NAMES_TABLE_ENTRY("amx-avx512", FEATURE_AMX_AVX512, P_NONE,
 			"-mamx-avx512")
+  ISA_NAMES_TABLE_ENTRY("amx-tf32", FEATURE_AMX_TF32, P_NONE, "-mamx-tf32")
 ISA_NAMES_TABLE_END
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 5d0240e..58fecf7 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -458,7 +458,7 @@ i[34567]86-*-* | x86_64-*-*)
 		       avx10_2bf16intrin.h avx10_2-512bf16intrin.h
 		       avx10_2satcvtintrin.h avx10_2-512satcvtintrin.h
 		       avx10_2minmaxintrin.h avx10_2-512minmaxintrin.h
-		       avx10_2copyintrin.h amxavx512intrin.h"
+		       avx10_2copyintrin.h amxavx512intrin.h amxtf32intrin.h"
 	;;
 ia64-*-*)
 	extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/amxtf32intrin.h b/gcc/config/i386/amxtf32intrin.h
new file mode 100644
index 0000000..450a33e
--- /dev/null
+++ b/gcc/config/i386/amxtf32intrin.h
@@ -0,0 +1,47 @@
+/* Copyright (C) 2024 Free Software Foundation, Inc.
+   This file is part of GCC.
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+#error "Never use <amxtf32intrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef _AMXTF32INTRIN_H_INCLUDED
+#define _AMXTF32INTRIN_H_INCLUDED
+
+#if !defined(__AMX_TF32__)
+#pragma GCC push_options
+#pragma GCC target("amx-tf32")
+#define __DISABLE_AMX_TF32__
+#endif /* __AMX_TF32__ */
+
+#if defined(__x86_64__)
+#define _tile_mmultf32ps_internal(src1_dst,src2,src3)			\
+  __asm__ volatile\
+  ("{tmmultf32ps\t%%tmm"#src3", %%tmm"#src2", %%tmm"#src1_dst"|tmmultf32ps\t%%tmm"#src1_dst", %%tmm"#src2", %%tmm"#src3"}" ::)
+
+#define _tile_mmultf32ps(src1_dst,src2,src3)				\
+  _tile_mmultf32ps_internal (src1_dst, src2, src3)
+
+#endif
+
+#ifdef __DISABLE_AMX_TF32__
+#undef __DISABLE_AMX_TF32__
+#pragma GCC pop_options
+#endif /* __DISABLE_AMX_TF32__ */
+
+#endif /* _AMXTF32INTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 2fc163b..7cd8319 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -164,6 +164,7 @@
 
 /* AMX sub leaf (%eax == 0x1e, %ecx == 1) */
 /* %eax */
+#define bit_AMX_TF32	(1 << 6)
 #define bit_AMX_AVX512  (1 << 7)
 
 /* AVX10 sub leaf (%eax == 0x24) */
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 1c36beb..98cb676 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -743,6 +743,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     def_or_undef (parse_in, "__AVX10_2_512__");
   if (isa_flag2 & OPTION_MASK_ISA2_AMX_AVX512)
     def_or_undef (parse_in, "__AMX_AVX512__");
+  if (isa_flag2 & OPTION_MASK_ISA2_AMX_TF32)
+    def_or_undef (parse_in, "__AMX_TF32__");
   if (TARGET_IAMCU)
     {
       def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index fcc3bc4..1b82a69 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -124,3 +124,4 @@ DEF_PTA(AVX10_1_512)
 DEF_PTA(AVX10_2_256)
 DEF_PTA(AVX10_2_512)
 DEF_PTA(AMX_AVX512)
+DEF_PTA(AMX_TF32)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 2f6646f..6f68e79 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -264,7 +264,8 @@ static struct ix86_target_opts isa2_opts[] =
   { "-mavx10.1-512",	OPTION_MASK_ISA2_AVX10_1_512 },
   { "-mavx10.2-256",	OPTION_MASK_ISA2_AVX10_2_256 },
   { "-mavx10.2-512",	OPTION_MASK_ISA2_AVX10_2_512 },
-  { "-mamx-avx512",	OPTION_MASK_ISA2_AMX_AVX512 }
+  { "-mamx-avx512",	OPTION_MASK_ISA2_AMX_AVX512 },
+  { "-mamx-tf32",	OPTION_MASK_ISA2_AMX_TF32 }
 };
 static struct ix86_target_opts isa_opts[] =
 {
@@ -1134,6 +1135,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
     IX86_ATTR_ISA ("avx10.2-256", OPT_mavx10_2_256),
     IX86_ATTR_ISA ("avx10.2-512", OPT_mavx10_2_512),
     IX86_ATTR_ISA ("amx-avx512", OPT_mamx_avx512),
+    IX86_ATTR_ISA ("amx-tf32", OPT_mamx_tf32),
 
     /* enum options */
     IX86_ATTR_ENUM ("fpmath=",	OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 232daff..280ad77 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1394,3 +1394,7 @@ mamx-avx512
 Target Mask(ISA2_AMX_AVX512) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.1-512,
 AVX10.2-512 and AMX-AVX512 built-in functions and code generation.
+
+mamx-tf32
+Target Mask(ISA2_AMX_TF32) Var(ix86_isa_flags2) Save
+Support AMX-TF32 built-in functions and code generation.
diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index 9f590f6..9921cda 100644
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -616,3 +616,6 @@ UrlSuffix(gcc/x86-Options.html#index-mavx10_002e2)
 mamx-avx512
 UrlSuffix(gcc/x86-Options.html#index-mamx-avx512)
 
+mamx-tf32
+UrlSuffix(gcc/x86-Options.html#index-mamx-tf32)
+
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 772af56..84b8f60 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -134,6 +134,8 @@
 
 #include <amxavx512intrin.h>
 
+#include <amxtf32intrin.h>
+
 #include <prfchwintrin.h>
 
 #include <keylockerintrin.h>
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index d2b3086..44cbe7c 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7549,6 +7549,11 @@ Enable/disable the generation of the AVX10.2 512 bit instructions.
 @itemx no-amx-avx512
 Enable/disable the generation of the AMX-AVX512 instructions.
 
+@cindex @code{target("amx-tf32")} function attribute, x86
+@item amx-tf32
+@itemx no-amx-tf32
+Enable/disable the generation of the AMX-TF32 instructions.
+
 @cindex @code{target("cld")} function attribute, x86
 @item cld
 @itemx no-cld
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1186bdd..15b7122 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1486,7 +1486,7 @@ See RS/6000 and PowerPC Options.
 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
 -musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 -mavx10.2 -mavx10.2-256
--mavx10.2-512 -mamx-avx512
+-mavx10.2-512 -mamx-avx512 -mamx-tf32
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg}
 -mkl -mwidekl
@@ -35677,6 +35677,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @need 200
 @opindex mamx-avx512
 @itemx -mamx-avx512
+@need 200
+@opindex mamx-tf32
+@itemx -mamx-tf32
 These switches enable the use of instructions in the MMX, SSE,
 AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, AES,
 PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
@@ -35687,9 +35690,9 @@ WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD,
 AVX512VPOPCNTDQ, AVX512VNNI, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8,
 AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16, AVXIFMA, AVXVNNIINT8, AVXNECONVERT,
 CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT, AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512,
-SM4, APX_F, USER_MSR, AVX10.1, AVX10.2, AMX-AVX512 or CLDEMOTE extended
-instruction sets. Each has a corresponding @option{-mno-} option to disable
-use of these instructions.
+SM4, APX_F, USER_MSR, AVX10.1, AVX10.2, AMX-AVX512, AMX-TF32 or CLDEMOTE
+extended instruction sets. Each has a corresponding @option{-mno-} option to
+disable use of these instructions.
 
 These extensions are also available as built-in functions: see
 @ref{x86 Built-in Functions}, for details of the functions enabled and
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 0dfbc57..5bb4bf1 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2653,6 +2653,9 @@ Target supports the execution of @code{amx-complex} instructions.
 @item amx_fp16
 Target supports the execution of @code{amx-fp16} instructions.
 
+@item amx_tf32
+Target supports the execution of @code{amx-tf32} instructions.
+
 @item cell_hw
 Test system can execute AltiVec and Cell PPU instructions.
 
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C
index 8e872f7..df985f1 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512 -mamx-avx512" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512 -mamx-avx512 -mamx-tf32" } */
 /* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib } } */
 
 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C
index 133e64f..0fa8bc7 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512 -mamx-avx512" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512 -mamx-avx512 -mamx-tf32" } */
 /* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib } } */
 
 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
diff --git a/gcc/testsuite/gcc.target/i386/amx-check.h b/gcc/testsuite/gcc.target/i386/amx-check.h
index a336392..e5e3522 100644
--- a/gcc/testsuite/gcc.target/i386/amx-check.h
+++ b/gcc/testsuite/gcc.target/i386/amx-check.h
@@ -222,6 +222,9 @@ main ()
 #ifdef AMX_AVX512
       && __builtin_cpu_supports ("amx-avx512")
 #endif
+#ifdef AMX_TF32
+      && __builtin_cpu_supports ("amx-tf32")
+#endif
 #ifdef __linux__
       && request_perm_xtile_data ()
 #endif
diff --git a/gcc/testsuite/gcc.target/i386/amx-helper.h b/gcc/testsuite/gcc.target/i386/amx-helper.h
index 847882d..0fdea0c 100644
--- a/gcc/testsuite/gcc.target/i386/amx-helper.h
+++ b/gcc/testsuite/gcc.target/i386/amx-helper.h
@@ -157,4 +157,25 @@ for (int j = 0; j < 32; j++)	\
     abort();			\
 }
 
+/* Mask low 13bits to zero */
+static float zero_lower_mantissa_bits_fp32 (float x)
+{
+  union32f_ud tmp;
+  tmp.f = x;
+  tmp.u = tmp.u & 0xffffe000;
+  return tmp.f;
+}
+
+/* Handle SNAN */
+static float silence_snan_fp32 (float x)
+{
+  union32f_ud tmp;
+  tmp.f = x;
+  if ((((tmp.u & 0x7f800000) >> 23) == 0xff) &&
+      ((tmp.u & 0x007fffff) != 0) &&
+      ((tmp.u & 0x00400000) == 0))
+    tmp.u = tmp.u | 0x00400000;
+  return tmp.f;
+}
+
 #endif
diff --git a/gcc/testsuite/gcc.target/i386/amxtf32-asmatt-1.c b/gcc/testsuite/gcc.target/i386/amxtf32-asmatt-1.c
new file mode 100644
index 0000000..3d184c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/amxtf32-asmatt-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mamx-tf32" } */
+/* { dg-final { scan-assembler "tmmultf32ps\[ \\t]+\[^\n\]*%tmm3+\[^\n\]*%tmm2+\[^\n\]*%tmm1"  } } */
+#include <immintrin.h>
+
+#define TMM1 1
+#define TMM2 2
+#define TMM3 3
+
+void TEST()
+{
+  _tile_mmultf32ps (TMM1, TMM2, TMM3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/amxtf32-asmintel-1.c b/gcc/testsuite/gcc.target/i386/amxtf32-asmintel-1.c
new file mode 100644
index 0000000..0188788
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/amxtf32-asmintel-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-require-effective-target masm_intel } */
+/* { dg-options "-O2 -mamx-tf32 -masm=intel" } */
+/* { dg-final { scan-assembler "tmmultf32ps\[ \\t]+\[^\n\]*%tmm1+\[^\n\]*%tmm2+\[^\n\]*%tmm3"  } } */
+#include <immintrin.h>
+
+void TEST()
+{
+  _tile_mmultf32ps (1, 2, 3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/amxtf32-mmultf32ps-2.c b/gcc/testsuite/gcc.target/i386/amxtf32-mmultf32ps-2.c
new file mode 100644
index 0000000..cf10bf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/amxtf32-mmultf32ps-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run { target { ! ia32 } } } */
+/* { dg-require-effective-target amx_tf32 } */
+/* { dg-options "-O2 -mamx-tf32" } */
+#define AMX_TF32
+#define DO_TEST test_amx_tf32_mmultf32ps
+void test_amx_tf32_mmultf32ps();
+#include "amx-helper.h"
+
+void calc_matrix_mmultf32ps (__tile *dst, __tile *src1, __tile *src2)
+{
+  float *src1_buf = (float *) src1->buf;
+  float *src2_buf = (float *) src2->buf;
+  float *dst_buf = (float *) dst->buf;
+
+  int M = src1->rows;
+  int K = src1->colsb / 4;
+  int N = src2->colsb / 4;
+  int m, n, k;
+
+  for (m = 0; m < M; m++)
+    for (k = 0; k < K; k++)
+      for (n = 0; n < N; n++)
+	dst_buf[m * N + n] +=
+	zero_lower_mantissa_bits_fp32 (silence_snan_fp32 (src1_buf[m * K + k])) *
+	zero_lower_mantissa_bits_fp32 (silence_snan_fp32 (src2_buf[k * N + n]));
+}
+
+void test_amx_tf32_mmultf32ps ()
+{
+  __tilecfg_u cfg;
+  __tile dst, dst_ref, src1, src2;
+  uint8_t tmp_dst_buf[1024];
+
+  init_fp32_max_tile_buffer (tmp_dst_buf);
+
+  init_tile_config (&cfg);
+  init_tile_reg_and_src_with_buffer (1, dst, tmp_dst_buf);
+  init_tile_reg_and_src_with_buffer (2, src1, tmp_dst_buf);
+  init_tile_reg_and_src_with_buffer (3, src2, tmp_dst_buf);
+
+  calc_matrix_mmultf32ps (&dst, &src1, &src2);
+
+  _tile_mmultf32ps (1, 2, 3);
+  _tile_stored (1, dst_ref.buf, _STRIDE);
+
+  if (!check_tile_register (&dst_ref, &dst))
+    abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index b4ffc5f..1ad4c1e 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -90,6 +90,7 @@ extern void test_user_msr (void)		__attribute__((__target__("usermsr")));
 extern void test_avx10_2 (void)			__attribute__((__target__("avx10.2")));
 extern void test_avx10_2_512 (void)		__attribute__((__target__("avx10.2-512")));
 extern void test_amx_avx512 (void)		__attribute__((__target__("amx-avx512")));
+extern void test_amx_tf32 (void)		__attribute__((__target__("amx-tf32")));
 
 extern void test_no_sgx (void)			__attribute__((__target__("no-sgx")));
 extern void test_no_avx512vpopcntdq(void)	__attribute__((__target__("no-avx512vpopcntdq")));
@@ -181,6 +182,7 @@ extern void test_no_user_msr (void)		__attribute__((__target__("no-usermsr")));
 extern void test_no_avx10_2 (void)		__attribute__((__target__("no-avx10.2")));
 extern void test_no_avx10_2_512 (void)		__attribute__((__target__("no-avx10.2-512")));
 extern void test_no_amx_avx512 (void)		__attribute__((__target__("no-amx-avx512")));
+extern void test_no_amx_tf32 (void)		__attribute__((__target__("no-amx-tf32")));
 
 extern void test_arch_nocona (void)		__attribute__((__target__("arch=nocona")));
 extern void test_arch_core2 (void)		__attribute__((__target__("arch=core2")));
diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c
index 3349ce0..7688ec3 100644
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -3,7 +3,7 @@
    popcntintrin.h gfniintrin.h and mm_malloc.h are usable
    with -O -std=c89 -pedantic-errors.  */
 /* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512 -mamx-avx512" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512 -mamx-avx512 -mamx-tf32" } */
 
 #include <x86intrin.h>
 
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index 9725cfe..c897b1a 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512 -mamx-avx512" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512 -mamx-avx512 -mamx-tf32" } */
 /* { dg-add-options bind_pic_locally } */
 
 #include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
index 13e636c..4866df3f 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512 -mamx-avx512" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512 -mamx-avx512 -mamx-tf32" } */
 /* { dg-add-options bind_pic_locally } */
 
 #include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
index 7c43c06..5d95a8b 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -103,7 +103,7 @@
 
 
 #ifndef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512,amx-avx512")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512,amx-avx512,amx-tf32")
 #endif
 
 /* Following intrinsics require immediate arguments.  They
@@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
 
 /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
 #ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512,amx-avx512")
+#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512,amx-avx512,amx-tf32")
 #endif
 #include <immintrin.h>
 test_1 (_cvtss_sh, unsigned short, float, 1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index 76e0d8d..edd1e1c 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -1082,6 +1082,6 @@
 #define __builtin_ia32_minmaxps128_mask(A, B, C, D, E) __builtin_ia32_minmaxps128_mask (A, B, 100, D, E)
 #define __builtin_ia32_minmaxps256_mask_round(A, B, C, D, E, F) __builtin_ia32_minmaxps256_mask_round (A, B, 100, D, E, 4)
 
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512,amx-avx512")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512,amx-avx512,amx-tf32")
 
 #include <x86intrin.h>
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 3b18269..dd166eb 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -10786,6 +10786,17 @@ proc check_effective_target_amx_avx512 { } {
     } "-mamx-avx512" ]
 }
 
+# Return 1 if amx-tf32 instructions can be compiled.
+proc check_effective_target_amx_tf32 { } {
+    return [check_no_compiler_messages amx_tf32 object {
+	void
+	foo ()
+	{
+	  __asm__ volatile ("tmmultf32ps\t%%tmm1, %%tmm2, %%tmm3" ::);
+	}
+    } "-mamx-tf32" ]
+}
+
 # Return 1 if sse instructions can be compiled.
 proc check_effective_target_sse { } {
     return [check_no_compiler_messages sse object {