RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 with GR2VR cost 0, 2 and 15

Add asm dump check test for vec_duplicate + vxor.vv combine to vxor.vx,
with the GR2VR cost is 0, 2 and 15.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
	for vxor.vx combine.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for vxor run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

33 files changed, 560 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index b15cb4c..b9be0f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index df3d3a3..2a84980 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index ed17b83..9c7ea5f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index aa11daf..fc23f1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 15db588..7e107d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index f15592c..f8ffab7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 80e32af..31d2945 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 9b19276..59e0334 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 596488c..de25086 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 8b4b7eb..5cac7c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 544c907..4b2885a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index af53f2b..e146831 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index a8ff915..9612e3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index d587a88..9641802 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index ff205d5..0d173e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index e8e2c7f..931295e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index bd38b86..d9e6e7b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index e0bdd22..13d219e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index aab3b4af..037a713 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 825988b..c97fff4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index a750510..24b4aa7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 2d279cf..0c1552a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 5a90883..8364f19 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 69af97a..8a31111 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index cd3cede..60f47f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -1966,4 +1966,396 @@ uint64_t TEST_BINARY_DATA(uint64_t, or)[][3][N] =
   },
 };
 
+int8_t TEST_BINARY_DATA(int8_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x2,  0x2,  0x2,  0x2,
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+    },
+    {
+       0x0,  0x0,  0x0,  0x0,
+       0x3,  0x3,  0x3,  0x3,
+       0x1,  0x1,  0x1,  0x1,
+      0xfe, 0xfe, 0xfe, 0xfe,
+    },
+  },
+  {
+    { 0x7f },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0x80, 0x80, 0x80, 0x80,
+       0xf,  0xf,  0xf,  0xf,
+      0x70, 0x70, 0x70, 0x70,
+    },
+    {
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+      0x70, 0x70, 0x70, 0x70,
+       0xf,  0xf,  0xf,  0xf,
+    },
+  },
+  {
+    { 0xf0 },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0x1f, 0x1f, 0x1f, 0x1f,
+      0x80, 0x80, 0x80, 0x80,
+       0x1,  0x1,  0x1,  0x1,
+    },
+    {
+       0xf,  0xf,  0xf,  0xf,
+      0xef, 0xef, 0xef, 0xef,
+      0x70, 0x70, 0x70, 0x70,
+      0xf1, 0xf1, 0xf1, 0xf1,
+    },
+  },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x2,    0x2,    0x2,    0x2,
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+    },
+    {
+         0x0,    0x0,    0x0,    0x0,
+         0x3,    0x3,    0x3,    0x3,
+         0x1,    0x1,    0x1,    0x1,
+      0xfffe, 0xfffe, 0xfffe, 0xfffe,
+    },
+  },
+  {
+    { 0x7fff },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0xf,    0xf,    0xf,    0xf,
+      0x7000, 0x7000, 0x7000, 0x7000,
+    },
+    {
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+      0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+      0x0fff, 0x0fff, 0x0fff, 0x0fff,
+    },
+  },
+  {
+    { 0xfff0 },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+        0x1f,   0x1f,   0x1f,   0x1f,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0x1,    0x1,    0x1,    0x1,
+    },
+    {
+         0xf,    0xf,    0xf,    0xf,
+      0xffef, 0xffef, 0xffef, 0xffef,
+      0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+      0xfff1, 0xfff1, 0xfff1, 0xfff1,
+    },
+  },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x2,        0x2,        0x2,        0x2,
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+    },
+    {
+             0x0,        0x0,        0x0,        0x0,
+             0x3,        0x3,        0x3,        0x3,
+             0x1,        0x1,        0x1,        0x1,
+      0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe,
+    },
+  },
+  {
+    { 0x7fffffff },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0xf,        0xf,        0xf,        0xf,
+      0x70000000, 0x70000000, 0x70000000, 0x70000000,
+    },
+    {
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+      0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+       0xfffffff,  0xfffffff,  0xfffffff,  0xfffffff,
+    },
+  },
+  {
+    { 0xfffffff0 },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+            0x1f,       0x1f,       0x1f,       0x1f,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0x1,        0x1,        0x1,        0x1,
+    },
+    {
+             0xf,        0xf,        0xf,        0xf,
+      0xffffffef, 0xffffffef, 0xffffffef, 0xffffffef,
+      0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+      0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1,
+    },
+  },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x2,                   0x2,                   0x2,                   0x2,
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+    },
+    {
+                        0x0,                   0x0,                   0x0,                   0x0,
+                        0x3,                   0x3,                   0x3,                   0x3,
+                        0x1,                   0x1,                   0x1,                   0x1,
+      0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull,
+    },
+  },
+  {
+    { 0x7fffffffffffffffull },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
+    },
+    {
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+      0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
+       0xfffffffffffffffull,  0xfffffffffffffffull,  0xfffffffffffffffull,  0xfffffffffffffffull,
+    },
+  },
+  {
+    { 0xfffffffffffffff0ull },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+                       0x1f,                  0x1f,                  0x1f,                  0x1f,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+    {
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull,
+      0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
+      0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull,
+    },
+  },
+};
+
+uint8_t TEST_BINARY_DATA(uint8_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x2,  0x2,  0x2,  0x2,
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+    },
+    {
+       0x0,  0x0,  0x0,  0x0,
+       0x3,  0x3,  0x3,  0x3,
+       0x1,  0x1,  0x1,  0x1,
+      0xfe, 0xfe, 0xfe, 0xfe,
+    },
+  },
+  {
+    { 0x7f },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0x80, 0x80, 0x80, 0x80,
+       0xf,  0xf,  0xf,  0xf,
+      0x70, 0x70, 0x70, 0x70,
+    },
+    {
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+      0x70, 0x70, 0x70, 0x70,
+       0xf,  0xf,  0xf,  0xf,
+    },
+  },
+  {
+    { 0xf0 },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0x1f, 0x1f, 0x1f, 0x1f,
+      0x80, 0x80, 0x80, 0x80,
+       0x1,  0x1,  0x1,  0x1,
+    },
+    {
+       0xf,  0xf,  0xf,  0xf,
+      0xef, 0xef, 0xef, 0xef,
+      0x70, 0x70, 0x70, 0x70,
+      0xf1, 0xf1, 0xf1, 0xf1,
+    },
+  },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x2,    0x2,    0x2,    0x2,
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+    },
+    {
+         0x0,    0x0,    0x0,    0x0,
+         0x3,    0x3,    0x3,    0x3,
+         0x1,    0x1,    0x1,    0x1,
+      0xfffe, 0xfffe, 0xfffe, 0xfffe,
+    },
+  },
+  {
+    { 0x7fff },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0xf,    0xf,    0xf,    0xf,
+      0x7000, 0x7000, 0x7000, 0x7000,
+    },
+    {
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+      0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+      0x0fff, 0x0fff, 0x0fff, 0x0fff,
+    },
+  },
+  {
+    { 0xfff0 },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+        0x1f,   0x1f,   0x1f,   0x1f,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0x1,    0x1,    0x1,    0x1,
+    },
+    {
+         0xf,    0xf,    0xf,    0xf,
+      0xffef, 0xffef, 0xffef, 0xffef,
+      0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+      0xfff1, 0xfff1, 0xfff1, 0xfff1,
+    },
+  },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x2,        0x2,        0x2,        0x2,
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+    },
+    {
+             0x0,        0x0,        0x0,        0x0,
+             0x3,        0x3,        0x3,        0x3,
+             0x1,        0x1,        0x1,        0x1,
+      0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe,
+    },
+  },
+  {
+    { 0x7fffffff },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0xf,        0xf,        0xf,        0xf,
+      0x70000000, 0x70000000, 0x70000000, 0x70000000,
+    },
+    {
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+      0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+       0xfffffff,  0xfffffff,  0xfffffff,  0xfffffff,
+    },
+  },
+  {
+    { 0xfffffff0 },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+            0x1f,       0x1f,       0x1f,       0x1f,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0x1,        0x1,        0x1,        0x1,
+    },
+    {
+             0xf,        0xf,        0xf,        0xf,
+      0xffffffef, 0xffffffef, 0xffffffef, 0xffffffef,
+      0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+      0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1,
+    },
+  },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, xor)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x2,                   0x2,                   0x2,                   0x2,
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+    },
+    {
+                        0x0,                   0x0,                   0x0,                   0x0,
+                        0x3,                   0x3,                   0x3,                   0x3,
+                        0x1,                   0x1,                   0x1,                   0x1,
+      0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull,
+    },
+  },
+  {
+    { 0x7fffffffffffffffull },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
+    },
+    {
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+      0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
+       0xfffffffffffffffull,  0xfffffffffffffffull,  0xfffffffffffffffull,  0xfffffffffffffffull,
+    },
+  },
+  {
+    { 0xfffffffffffffff0ull },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+                       0x1f,                  0x1f,                  0x1f,                  0x1f,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+    {
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull,
+      0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
+      0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull,
+    },
+  },
+};
+
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c
new file mode 100644
index 0000000..8441720
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int16_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c
new file mode 100644
index 0000000..cdb773f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int32_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c
new file mode 100644
index 0000000..8618b9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int64_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c
new file mode 100644
index 0000000..13724ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int8_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c
new file mode 100644
index 0000000..e6030f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint16_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c
new file mode 100644
index 0000000..cdb773f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int32_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c
new file mode 100644
index 0000000..44f0fff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint64_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c
new file mode 100644
index 0000000..2e983e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint8_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"