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| author | liuhongt <hongtao.liu@intel.com> | 2024-06-03 10:38:19 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2024-06-14 14:53:25 +0800 |
| commit | 8b69efd9819f86b973d7a550e987ce455fce6d62 (patch) | |
| tree | 277073b47767551b7cab28437bee11c94862f21c | |
| parent | c129a34dc8e69f7b34cf72835aeba2cefbb8673a (diff) | |
| download | gcc-8b69efd9819f86b973d7a550e987ce455fce6d62.zip gcc-8b69efd9819f86b973d7a550e987ce455fce6d62.tar.gz gcc-8b69efd9819f86b973d7a550e987ce455fce6d62.tar.bz2 | |
Remove one_if_conv for latest Intel processors.
The tune is added by PR79390 for SciMark2 on Broadwell.
For latest GCC, with and without the -mtune-ctrl=^one_if_conv_insn.
GCC will generate the same binary for SciMark2. And for SPEC2017,
there's no big impact for SKX/CLX/ICX, and small improvements on SPR
and later.
gcc/ChangeLog:
* config/i386/x86-tune.def (X86_TUNE_ONE_IF_CONV_INSN): Remove
latest Intel processors.
Co-authored by: Lingling Kong <lingling.kong@intel.com>
| -rw-r--r-- | gcc/config/i386/x86-tune.def | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 0fa1484..6651299 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -346,8 +346,8 @@ DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4) /* X86_TUNE_ONE_IF_CONV_INSNS: Restrict a number of cmov insns in if-converted sequence to one. */ DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn", - m_SILVERMONT | m_INTEL | m_CORE_ALL | m_GOLDMONT | m_GOLDMONT_PLUS - | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_ZHAOXIN | m_GENERIC) + m_SILVERMONT | m_HASWELL | m_SKYLAKE | m_GOLDMONT | m_GOLDMONT_PLUS + | m_TREMONT | m_ZHAOXIN) /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */ DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence", |