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authorEric Botcazou <ebotcazou@libertysurf.fr>2003-05-31 09:53:13 +0200
committerEric Botcazou <ebotcazou@gcc.gnu.org>2003-05-31 07:53:13 +0000
commit8a69f99fc9ba625676c93c510e1302fae80874f6 (patch)
treebf34282f98f8bf14d3c74c82baa0ef43ba84fe9d
parent68e4d4c56e56823001a8cd0a1f4506aab0546d3d (diff)
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md.texi (Machine Constraints): Document missing SPARC constraints.
* doc/md.texi (Machine Constraints): Document missing SPARC constraints. From-SVN: r67263
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/doc/md.texi16
2 files changed, 21 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 18bc820..05ba8ae 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
2003-05-31 Eric Botcazou <ebotcazou@libertysurf.fr>
+ * doc/md.texi (Machine Constraints): Document
+ missing SPARC constraints.
+
+2003-05-31 Eric Botcazou <ebotcazou@libertysurf.fr>
+
* doc/md.texi (Automaton pipeline description): Use
"type" instead of "cpu" as the attribute in the examples.
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 0ef948a..665e349 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2020,6 +2020,22 @@ Floating-point register that can hold 32- or 64-bit values.
@item e
Floating-point register that can hold 64- or 128-bit values.
+@item c
+Floating-point condition code register.
+
+@item d
+Floating-point register that can hold 32- or 64-bit values.
+It is only valid on the SPARC-V9 architecture when the Visual
+Instructions Set is available.
+
+@item b
+Floating-point register that can hold 64- or 128-bit values.
+It is only valid on the SPARC-V9 architecture when the Visual
+Instructions Set is available.
+
+@item h
+64-bit global or out register for the SPARC-V8+ architecture.
+
@item I
Signed 13-bit constant