re PR rtl-optimization/23098 (store of 0.0 to float)

        PR rtl-optimization/23098
        * config/rs6000/predicates.md (easy_fp_constant): SFmode constant
        0.0f is easy.
        * config/rs6000/rs6000.md (movdf splitter): Use
        const_double_operand predicate for TARGET_POWERPC64.
        * config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Expand
        SYMBOL_REF method to ABI_V4.

        * config/rs6000/altivec.md (build_vector_mask_for_load): Use
        replace_equiv_address.
        * config/rs6000/rs6000.c (rs6000_emit_eh_reg_restore): Mark MEM as
        rs6000_sr_alias_set and MEM_NOTRAP.
        (rs6000_aix_emit_builtin_unwind_init): Use gen_frame_mem().

From-SVN: r104145

5 files changed, 43 insertions, 13 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d763ece..2501c1a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2005-09-11  David Edelsohn  <edelsohn@gnu.org>
+
+	PR rtl-optimization/23098
+	* config/rs6000/predicates.md (easy_fp_constant): SFmode constant
+	0.0f is easy.
+	* config/rs6000/rs6000.md (movdf splitter): Use
+	const_double_operand predicate for TARGET_POWERPC64.
+	* config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Expand
+	SYMBOL_REF method to ABI_V4.
+
+	* config/rs6000/altivec.md (build_vector_mask_for_load): Use
+	replace_equiv_address.
+	* config/rs6000/rs6000.c (rs6000_emit_eh_reg_restore): Mark MEM as
+	rs6000_sr_alias_set and MEM_NOTRAP.
+	(rs6000_aix_emit_builtin_unwind_init): Use gen_frame_mem().
+
 2005-09-11  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* tree.c (contains_placeholder_p) <tcc_expression>: Properly
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 9016b0d..056a816 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1838,7 +1838,7 @@
   emit_insn (gen_rtx_SET (VOIDmode, temp, 
 			  gen_rtx_NEG (GET_MODE (addr), addr)));
   emit_insn (gen_altivec_lvsr (operands[0], 
-			       gen_rtx_MEM (GET_MODE (operands[1]), temp)));
+			       replace_equiv_address (operands[1], temp)));
   DONE;
 }")
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 64304e5..ff47505 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -235,6 +235,10 @@
 	      && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
 
     case SFmode:
+      /* The constant 0.f is easy.  */
+      if (op == CONST0_RTX (SFmode))
+	return 1;
+
       /* Force constants to memory before reload to utilize
 	 compress_float_constant.
 	 Avoid this when flag_unsafe_math_optimizations is enabled
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 6cc10ec..4454813 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -3245,16 +3245,21 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
       return x;
     }
 
-#if TARGET_MACHO
   if (GET_CODE (x) == SYMBOL_REF
-      && DEFAULT_ABI == ABI_DARWIN
       && !ALTIVEC_VECTOR_MODE (mode)
+#if TARGET_MACHO
+      && DEFAULT_ABI == ABI_DARWIN
       && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
+#else
+      && DEFAULT_ABI == ABI_V4
+      && !flag_pic
+#endif
       /* Don't do this for TFmode, since the result isn't offsettable.
 	 The same goes for DImode without 64-bit gprs.  */
       && mode != TFmode
       && (mode != DImode || TARGET_POWERPC64))
     {
+#if TARGET_MACHO
       if (flag_pic)
 	{
 	  rtx offset = gen_rtx_CONST (Pmode,
@@ -3265,6 +3270,7 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
 		  gen_rtx_HIGH (Pmode, offset)), offset);
 	}
       else
+#endif
 	x = gen_rtx_LO_SUM (GET_MODE (x),
 	      gen_rtx_HIGH (Pmode, x), x);
 
@@ -3274,7 +3280,6 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
       *win = 1;
       return x;
     }
-#endif
 
   /* Reload an offset address wrapped by an AND that represents the
      masking of the lower bits.  Strip the outer AND and let reload
@@ -13368,7 +13373,10 @@ rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
 	  || current_function_calls_alloca
 	  || info->total_size > 32767)
 	{
-	  emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
+	  tmp = gen_rtx_MEM (Pmode, frame_rtx);
+	  MEM_NOTRAP_P (tmp) = 1;
+	  set_mem_alias_set (tmp, rs6000_sr_alias_set);
+	  emit_move_insn (operands[1], tmp);
 	  frame_rtx = operands[1];
 	}
       else if (info->push_p)
@@ -13376,6 +13384,8 @@ rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
 
       tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
       tmp = gen_rtx_MEM (Pmode, tmp);
+      MEM_NOTRAP_P (tmp) = 1;
+      set_mem_alias_set (tmp, rs6000_sr_alias_set);
       emit_move_insn (tmp, operands[0]);
     }
   else
@@ -13448,12 +13458,12 @@ rs6000_aix_emit_builtin_unwind_init (void)
   rtx tocompare = gen_reg_rtx (SImode);
   rtx no_toc_save_needed = gen_label_rtx ();
 
-  mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
+  mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
   emit_move_insn (stack_top, mem);
 
-  mem = gen_rtx_MEM (Pmode,
-		     gen_rtx_PLUS (Pmode, stack_top,
-				   GEN_INT (2 * GET_MODE_SIZE (Pmode))));
+  mem = gen_frame_mem (Pmode,
+		       gen_rtx_PLUS (Pmode, stack_top,
+				     GEN_INT (2 * GET_MODE_SIZE (Pmode))));
   emit_move_insn (opcode_addr, mem);
   emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
   emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
@@ -13463,9 +13473,9 @@ rs6000_aix_emit_builtin_unwind_init (void)
 			   SImode, NULL_RTX, NULL_RTX,
 			   no_toc_save_needed);
 
-  mem = gen_rtx_MEM (Pmode,
-		     gen_rtx_PLUS (Pmode, stack_top,
-				   GEN_INT (5 * GET_MODE_SIZE (Pmode))));
+  mem = gen_frame_mem (Pmode,
+		       gen_rtx_PLUS (Pmode, stack_top,
+				     GEN_INT (5 * GET_MODE_SIZE (Pmode))));
   emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
   emit_label (no_toc_save_needed);
 }
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d8332e3..46381dc 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7495,7 +7495,7 @@
 
 (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(match_operand:DF 1 "easy_fp_constant" ""))]
+	(match_operand:DF 1 "const_double_operand" ""))]
   "TARGET_POWERPC64 && reload_completed
    && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG