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| author | Kewen Lin <linkw@linux.ibm.com> | 2020-12-02 01:55:34 -0600 |
|---|---|---|
| committer | Kewen Lin <linkw@linux.ibm.com> | 2020-12-02 01:55:34 -0600 |
| commit | 82800987cb3b22427a8799b3e8491eff496724b9 (patch) | |
| tree | 54520e860d55b30126d5a2f5afb2f28461638b6a | |
| parent | 018248ef6d03ca0088d5928928f966df99af134c (diff) | |
| download | gcc-82800987cb3b22427a8799b3e8491eff496724b9.zip gcc-82800987cb3b22427a8799b3e8491eff496724b9.tar.gz gcc-82800987cb3b22427a8799b3e8491eff496724b9.tar.bz2 | |
rs6000: Disable HTM for Power10 and later by default
Power ISA 3.1 has dropped transactional memory support, this patch
is to disable HTM feature for power10 and later by default.
Bootstrapped/regtested on powerpc64le-linux-gnu P8 and P10.
gcc/ChangeLog:
* config/rs6000/rs6000.c (rs6000_option_override_internal):
Use OPTION_MASK_DIRECT_MOVE for Power8 target_enable instead
of OPTION_MASK_HTM.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER):
Remove OPTION_MASK_HTM.
(RS6000_CPU): Add OPTION_MASK_HTM to power8, power9 and
powerpc64le entries.
| -rw-r--r-- | gcc/config/rs6000/rs6000-cpus.def | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 5 |
2 files changed, 9 insertions, 6 deletions
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 8d2c1ff..482e1b6 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -51,7 +51,6 @@ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DIRECT_MOVE \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ - | OPTION_MASK_HTM \ | OPTION_MASK_QUAD_MEMORY \ | OPTION_MASK_QUAD_MEMORY_ATOMIC) @@ -240,10 +239,13 @@ RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) -RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) -RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER) +RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER + | OPTION_MASK_HTM) +RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER + | OPTION_MASK_HTM) RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) +RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER + | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 517467e..c661f7a 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3808,9 +3808,10 @@ rs6000_option_override_internal (bool global_init_p) } /* If little-endian, default to -mstrict-align on older processors. - Testing for htm matches power8 and later. */ + Testing for direct_move matches power8 and later. */ if (!BYTES_BIG_ENDIAN - && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) + && !(processor_target_table[tune_index].target_enable + & OPTION_MASK_DIRECT_MOVE)) rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; if (!rs6000_fold_gimple) |