diff options
author | Richard Sandiford <richard.sandiford@linaro.org> | 2018-01-13 17:50:45 +0000 |
---|---|---|
committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2018-01-13 17:50:45 +0000 |
commit | 801e38459d49a0b55eacc5013e5692394dd290d2 (patch) | |
tree | 7f453a85051e7ebbe900827b47163a71d13b505a | |
parent | 43cacb12fc859b671464b63668794158974b2a34 (diff) | |
download | gcc-801e38459d49a0b55eacc5013e5692394dd290d2.zip gcc-801e38459d49a0b55eacc5013e5692394dd290d2.tar.gz gcc-801e38459d49a0b55eacc5013e5692394dd290d2.tar.bz2 |
[AArch64] Testsuite markup for SVE
This patch adds new target selectors for SVE and updates existing
selectors accordingly. It also XFAILs some tests that don't yet
work for some SVE modes; most of these go away with follow-on
vectorisation enhancements.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_aarch64_sve)
(aarch64_sve_bits, check_effective_target_aarch64_sve_hw)
(aarch64_sve_hw_bits, check_effective_target_aarch64_sve256_hw):
New procedures.
(check_effective_target_vect_perm): Handle SVE.
(check_effective_target_vect_perm_byte): Likewise.
(check_effective_target_vect_perm_short): Likewise.
(check_effective_target_vect_widen_sum_hi_to_si_pattern): Likewise.
(check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
(check_effective_target_vect_widen_mult_hi_to_si): Likewise.
(check_effective_target_vect_element_align_preferred): Likewise.
(check_effective_target_vect_align_stack_vars): Likewise.
(check_effective_target_vect_load_lanes): Likewise.
(check_effective_target_vect_masked_store): Likewise.
(available_vector_sizes): Use aarch64_sve_bits for SVE.
* gcc.dg/vect/tree-vect.h (VECTOR_BITS): Define appropriately
for SVE.
* gcc.dg/tree-ssa/ssa-dom-cse-2.c: Add SVE XFAIL.
* gcc.dg/vect/bb-slp-pr69907.c: Likewise.
* gcc.dg/vect/no-vfa-vect-depend-2.c: Likewise.
* gcc.dg/vect/no-vfa-vect-depend-3.c: Likewise.
* gcc.dg/vect/slp-23.c: Likewise.
* gcc.dg/vect/slp-perm-5.c: Likewise.
* gcc.dg/vect/slp-perm-6.c: Likewise.
* gcc.dg/vect/slp-perm-9.c: Likewise.
* gcc.dg/vect/slp-reduc-3.c: Likewise.
* gcc.dg/vect/vect-114.c: Likewise.
* gcc.dg/vect/vect-mult-const-pattern-1.c: Likewise.
* gcc.dg/vect/vect-mult-const-pattern-2.c: Likewise.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256613
-rw-r--r-- | gcc/testsuite/ChangeLog | 34 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-2.c | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-3.c | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/slp-23.c | 4 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/slp-perm-5.c | 4 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/slp-perm-6.c | 4 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/slp-perm-9.c | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/slp-reduc-3.c | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/tree-vect.h | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/vect-114.c | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-1.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-2.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 104 |
15 files changed, 172 insertions, 23 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3a8791e..0ad46ee 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,4 +1,38 @@ 2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> + Alan Hayward <alan.hayward@arm.com> + David Sherwood <david.sherwood@arm.com> + + * lib/target-supports.exp (check_effective_target_aarch64_sve) + (aarch64_sve_bits, check_effective_target_aarch64_sve_hw) + (aarch64_sve_hw_bits, check_effective_target_aarch64_sve256_hw): + New procedures. + (check_effective_target_vect_perm): Handle SVE. + (check_effective_target_vect_perm_byte): Likewise. + (check_effective_target_vect_perm_short): Likewise. + (check_effective_target_vect_widen_sum_hi_to_si_pattern): Likewise. + (check_effective_target_vect_widen_mult_qi_to_hi): Likewise. + (check_effective_target_vect_widen_mult_hi_to_si): Likewise. + (check_effective_target_vect_element_align_preferred): Likewise. + (check_effective_target_vect_align_stack_vars): Likewise. + (check_effective_target_vect_load_lanes): Likewise. + (check_effective_target_vect_masked_store): Likewise. + (available_vector_sizes): Use aarch64_sve_bits for SVE. + * gcc.dg/vect/tree-vect.h (VECTOR_BITS): Define appropriately + for SVE. + * gcc.dg/tree-ssa/ssa-dom-cse-2.c: Add SVE XFAIL. + * gcc.dg/vect/bb-slp-pr69907.c: Likewise. + * gcc.dg/vect/no-vfa-vect-depend-2.c: Likewise. + * gcc.dg/vect/no-vfa-vect-depend-3.c: Likewise. + * gcc.dg/vect/slp-23.c: Likewise. + * gcc.dg/vect/slp-perm-5.c: Likewise. + * gcc.dg/vect/slp-perm-6.c: Likewise. + * gcc.dg/vect/slp-perm-9.c: Likewise. + * gcc.dg/vect/slp-reduc-3.c: Likewise. + * gcc.dg/vect/vect-114.c: Likewise. + * gcc.dg/vect/vect-mult-const-pattern-1.c: Likewise. + * gcc.dg/vect/vect-mult-const-pattern-2.c: Likewise. + +2018-01-13 Richard Sandiford <richard.sandiford@linaro.org> * gcc.dg/vect/no-scevccp-slp-30.c: XFAIL SLP test for vect_variable_length, expecting the test to be vectorized diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c index 7e88516..7e77a6a 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c @@ -25,4 +25,4 @@ foo () but the loop reads only one element at a time, and DOM cannot resolve these. The same happens on powerpc depending on the SIMD support available. */ -/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* nvptx*-*-* } || { lp64 && { powerpc*-*-* sparc*-*-* riscv*-*-* } } } } } } */ +/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* nvptx*-*-* } || { { lp64 && { powerpc*-*-* sparc*-*-* riscv*-*-* } } || aarch64_sve } } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c index 7e4a452..85f9a02 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c @@ -17,4 +17,6 @@ void foo(unsigned *p1, unsigned short *p2) p1[n] = p2[n * 2]; } -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" } } */ +/* Disable for SVE because for long or variable-length vectors we don't + get an unrolled epilogue loop. */ +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { ! aarch64_sve } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-2.c b/gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-2.c index 2271163..acad8fc 100644 --- a/gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-2.c +++ b/gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-2.c @@ -51,4 +51,7 @@ int main (void) } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {xfail { vect_no_align && { ! vect_hw_misalign } } } } } */ -/* { dg-final { scan-tree-dump-times "dependence distance negative" 1 "vect" } } */ +/* Requires reverse for variable-length SVE, which is implemented for + by a later patch. Until then we report it twice, once for SVE and + once for 128-bit Advanced SIMD. */ +/* { dg-final { scan-tree-dump-times "dependence distance negative" 1 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-3.c b/gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-3.c index cd0eb84..1ccfc1e 100644 --- a/gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-3.c +++ b/gcc/testsuite/gcc.dg/vect/no-vfa-vect-depend-3.c @@ -183,4 +183,7 @@ int main () } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" {xfail { vect_no_align && { ! vect_hw_misalign } } } } } */ -/* { dg-final { scan-tree-dump-times "dependence distance negative" 4 "vect" } } */ +/* f4 requires reverse for SVE, which is implemented by a later patch. + Until then we report it twice, once for SVE and once for 128-bit + Advanced SIMD. */ +/* { dg-final { scan-tree-dump-times "dependence distance negative" 4 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-23.c b/gcc/testsuite/gcc.dg/vect/slp-23.c index 0acb37e..88708e6 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-23.c +++ b/gcc/testsuite/gcc.dg/vect/slp-23.c @@ -107,6 +107,8 @@ int main (void) /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided8 && { ! { vect_no_align} } } } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided8 || vect_no_align } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_perm } } } } */ +/* We fail to vectorize the second loop with variable-length SVE but + fall back to 128-bit vectors, which does use SLP. */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_perm } xfail aarch64_sve } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_perm } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-5.c b/gcc/testsuite/gcc.dg/vect/slp-perm-5.c index 7e132e1..e076008 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-perm-5.c +++ b/gcc/testsuite/gcc.dg/vect/slp-perm-5.c @@ -104,7 +104,9 @@ int main (int argc, const char* argv[]) } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_perm } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } } } } */ +/* Fails for variable-length SVE because we fall back to Advanced SIMD + and use LD3/ST3. Will be fixed when SVE LOAD_LANES support is added. */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target vect_load_lanes } } } */ /* { dg-final { scan-tree-dump "note: Built SLP cancelled: can use load/store-lanes" "vect" { target { vect_perm3_int && vect_load_lanes } } } } */ /* { dg-final { scan-tree-dump "LOAD_LANES" "vect" { target vect_load_lanes } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-6.c b/gcc/testsuite/gcc.dg/vect/slp-perm-6.c index f97887f..3ee2b92 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-perm-6.c +++ b/gcc/testsuite/gcc.dg/vect/slp-perm-6.c @@ -103,7 +103,9 @@ int main (int argc, const char* argv[]) } /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_perm } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } } } } */ +/* Fails for variable-length SVE because we fall back to Advanced SIMD + and use LD3/ST3. Will be fixed when SVE LOAD_LANES support is added. */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_load_lanes } } } */ /* { dg-final { scan-tree-dump "note: Built SLP cancelled: can use load/store-lanes" "vect" { target { vect_perm3_int && vect_load_lanes } } } } */ /* { dg-final { scan-tree-dump "LOAD_LANES" "vect" { target vect_load_lanes } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-9.c b/gcc/testsuite/gcc.dg/vect/slp-perm-9.c index 0b54b3b..f701079 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-perm-9.c +++ b/gcc/testsuite/gcc.dg/vect/slp-perm-9.c @@ -57,10 +57,11 @@ int main (int argc, const char* argv[]) return 0; } -/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 2 "vect" { target { ! { vect_perm_short || vect_load_lanes } } } } } */ +/* Fails for variable-length SVE because we fall back to Advanced SIMD + and use LD3/ST3. Will be fixed when SVE LOAD_LANES support is added. */ +/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 2 "vect" { target { ! { vect_perm_short || vect_load_lanes } } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_perm_short || vect_load_lanes } } } } */ /* { dg-final { scan-tree-dump-times "permutation requires at least three vectors" 1 "vect" { target { vect_perm_short && { ! vect_perm3_short } } } } } */ /* { dg-final { scan-tree-dump-not "permutation requires at least three vectors" "vect" { target vect_perm3_short } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { { ! vect_perm3_short } || vect_load_lanes } } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_perm3_short && { ! vect_load_lanes } } } } } */ - diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-3.c b/gcc/testsuite/gcc.dg/vect/slp-reduc-3.c index 511fff5..34c8da7 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-reduc-3.c +++ b/gcc/testsuite/gcc.dg/vect/slp-reduc-3.c @@ -58,4 +58,7 @@ int main (void) /* The initialization loop in main also gets vectorized. */ /* { dg-final { scan-tree-dump-times "vect_recog_dot_prod_pattern: detected" 1 "vect" { xfail *-*-* } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_short_mult && { vect_widen_sum_hi_to_si && vect_unpack } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_widen_sum_hi_to_si_pattern || { ! vect_unpack } } } } } */ +/* We can't yet create the necessary SLP constant vector for variable-length + SVE and so fall back to Advanced SIMD. This means that we repeat each + analysis note. */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_widen_sum_hi_to_si_pattern || { { ! vect_unpack } || { aarch64_sve && vect_variable_length } } } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h index 8813537..69c93ac 100644 --- a/gcc/testsuite/gcc.dg/vect/tree-vect.h +++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h @@ -76,4 +76,12 @@ check_vect (void) signal (SIGILL, SIG_DFL); } -#define VECTOR_BITS 128 +#if defined (__ARM_FEATURE_SVE) +# if __ARM_FEATURE_SVE_BITS == 0 +# define VECTOR_BITS 1024 +# else +# define VECTOR_BITS __ARM_FEATURE_SVE_BITS +# endif +#else +# define VECTOR_BITS 128 +#endif diff --git a/gcc/testsuite/gcc.dg/vect/vect-114.c b/gcc/testsuite/gcc.dg/vect/vect-114.c index 929c804..557b441 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-114.c +++ b/gcc/testsuite/gcc.dg/vect/vect-114.c @@ -34,6 +34,9 @@ int main (void) return main1 (); } -/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_perm } } } } } */ +/* Requires reverse for SVE, which is implemented by a later patch. + Until then we fall back to Advanced SIMD and successfully vectorize + the loop. */ +/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_perm } xfail { aarch64_sve && vect_variable_length } } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_perm } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-1.c b/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-1.c index e5dba82..ee34eea 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-1.c +++ b/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-1.c @@ -37,5 +37,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* } } } */ +/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* xfail aarch64_sve } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target aarch64*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-2.c b/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-2.c index c5beaba..fbd6c90 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-2.c +++ b/gcc/testsuite/gcc.dg/vect/vect-mult-const-pattern-2.c @@ -36,5 +36,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* } } } */ +/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* xfail aarch64_sve } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target aarch64*-*-* } } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 8ad3435..f525426 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3340,6 +3340,35 @@ proc check_effective_target_aarch64_little_endian { } { }] } +# Return 1 if this is an AArch64 target supporting SVE. +proc check_effective_target_aarch64_sve { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_no_compiler_messages aarch64_sve assembly { + #if !defined (__ARM_FEATURE_SVE) + #error FOO + #endif + }] +} + +# Return the size in bits of an SVE vector, or 0 if the size is variable. +proc aarch64_sve_bits { } { + return [check_cached_effective_target aarch64_sve_bits { + global tool + + set src dummy[pid].c + set f [open $src "w"] + puts $f "int bits = __ARM_FEATURE_SVE_BITS;" + close $f + set output [${tool}_target_compile $src "" preprocess ""] + file delete $src + + regsub {.*bits = ([^;]*);.*} $output {\1} bits + expr { $bits } + }] +} + # Return 1 if this is a compiler supporting ARC atomic operations proc check_effective_target_arc_atomic { } { return [check_no_compiler_messages arc_atomic assembly { @@ -4278,6 +4307,49 @@ proc check_effective_target_arm_neon_hw { } { } [add_options_for_arm_neon ""]] } +# Return true if this is an AArch64 target that can run SVE code. + +proc check_effective_target_aarch64_sve_hw { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_runtime aarch64_sve_hw_available { + int + main (void) + { + asm volatile ("ptrue p0.b"); + return 0; + } + }] +} + +# Return true if this is an AArch64 target that can run SVE code and +# if its SVE vectors have exactly BITS bits. + +proc aarch64_sve_hw_bits { bits } { + if { ![check_effective_target_aarch64_sve_hw] } { + return 0 + } + return [check_runtime aarch64_sve${bits}_hw [subst { + int + main (void) + { + int res; + asm volatile ("cntd %0" : "=r" (res)); + if (res * 64 != $bits) + __builtin_abort (); + return 0; + } + }]] +} + +# Return true if this is an AArch64 target that can run SVE code and +# if its SVE vectors have exactly 256 bits. + +proc check_effective_target_aarch64_sve256_hw { } { + return [aarch64_sve_hw_bits 256] +} + proc check_effective_target_arm_neonv2_hw { } { return [check_runtime arm_neon_hwv2_available { #include "arm_neon.h" @@ -5579,7 +5651,8 @@ proc check_effective_target_vect_perm { } { } else { set et_vect_perm_saved($et_index) 0 if { [is-effective-target arm_neon] - || [istarget aarch64*-*-*] + || ([istarget aarch64*-*-*] + && ![check_effective_target_vect_variable_length]) || [istarget powerpc*-*-*] || [istarget spu-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] @@ -5684,7 +5757,8 @@ proc check_effective_target_vect_perm_byte { } { if { ([is-effective-target arm_neon] && [is-effective-target arm_little_endian]) || ([istarget aarch64*-*-*] - && [is-effective-target aarch64_little_endian]) + && [is-effective-target aarch64_little_endian] + && ![check_effective_target_vect_variable_length]) || [istarget powerpc*-*-*] || [istarget spu-*-*] || ([istarget mips-*.*] @@ -5723,7 +5797,8 @@ proc check_effective_target_vect_perm_short { } { if { ([is-effective-target arm_neon] && [is-effective-target arm_little_endian]) || ([istarget aarch64*-*-*] - && [is-effective-target aarch64_little_endian]) + && [is-effective-target aarch64_little_endian] + && ![check_effective_target_vect_variable_length]) || [istarget powerpc*-*-*] || [istarget spu-*-*] || ([istarget mips*-*-*] @@ -5783,7 +5858,8 @@ proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } { } else { set et_vect_widen_sum_hi_to_si_pattern_saved($et_index) 0 if { [istarget powerpc*-*-*] - || [istarget aarch64*-*-*] + || ([istarget aarch64*-*-*] + && ![check_effective_target_aarch64_sve]) || [is-effective-target arm_neon] || [istarget ia64-*-*] } { set et_vect_widen_sum_hi_to_si_pattern_saved($et_index) 1 @@ -5895,7 +5971,8 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } { set et_vect_widen_mult_qi_to_hi_saved($et_index) 0 } if { [istarget powerpc*-*-*] - || [istarget aarch64*-*-*] + || ([istarget aarch64*-*-*] + && ![check_effective_target_aarch64_sve]) || [is-effective-target arm_neon] || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) } { @@ -5933,7 +6010,8 @@ proc check_effective_target_vect_widen_mult_hi_to_si { } { if { [istarget powerpc*-*-*] || [istarget spu-*-*] || [istarget ia64-*-*] - || [istarget aarch64*-*-*] + || ([istarget aarch64*-*-*] + && ![check_effective_target_aarch64_sve]) || [istarget i?86-*-*] || [istarget x86_64-*-*] || [is-effective-target arm_neon] || ([istarget s390*-*-*] @@ -6420,12 +6498,16 @@ proc check_effective_target_vect_natural_alignment { } { # alignment during vectorization. proc check_effective_target_vect_element_align_preferred { } { - return [check_effective_target_vect_variable_length] + return [expr { [check_effective_target_aarch64_sve] + && [check_effective_target_vect_variable_length] }] } # Return 1 if we can align stack data to the preferred vector alignment. proc check_effective_target_vect_align_stack_vars { } { + if { [check_effective_target_aarch64_sve] } { + return [check_effective_target_vect_variable_length] + } return 1 } @@ -6497,7 +6579,8 @@ proc check_effective_target_vect_load_lanes { } { } else { set et_vect_load_lanes 0 if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) - || [istarget aarch64*-*-*] } { + || ([istarget aarch64*-*-*] + && ![check_effective_target_aarch64_sve]) } { set et_vect_load_lanes 1 } } @@ -6509,7 +6592,7 @@ proc check_effective_target_vect_load_lanes { } { # Return 1 if the target supports vector masked stores. proc check_effective_target_vect_masked_store { } { - return 0 + return [check_effective_target_aarch64_sve] } # Return 1 if the target supports vector conditional operations, 0 otherwise. @@ -6777,6 +6860,9 @@ foreach N {2 3 4 8} { proc available_vector_sizes { } { set result {} if { [istarget aarch64*-*-*] } { + if { [check_effective_target_aarch64_sve] } { + lappend result [aarch64_sve_bits] + } lappend result 128 64 } elseif { [istarget arm*-*-*] && [check_effective_target_arm_neon_ok] } { |