diff options
author | David Ung <davidu@mips.com> | 2005-07-29 17:25:27 +0000 |
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committer | David Ung <davidu@gcc.gnu.org> | 2005-07-29 17:25:27 +0000 |
commit | 79dad081a1117381afd19a2f62438766a3bee859 (patch) | |
tree | 3b430ef3b3b488bc0171dd342af719c0bf136a97 | |
parent | 89e80dd49573d8eda808fb2a5dd09546329f8e82 (diff) | |
download | gcc-79dad081a1117381afd19a2f62438766a3bee859.zip gcc-79dad081a1117381afd19a2f62438766a3bee859.tar.gz gcc-79dad081a1117381afd19a2f62438766a3bee859.tar.bz2 |
mips.c (mips_cpu_info_table): Add 5kf to the table.
* config/mips/mips.c (mips_cpu_info_table): Add 5kf to the table.
(mips_rtx_cost_data): Add costs for 5kc and 5kf.
* config/mips/mips.h (processor_type): Add PROCESSOR_5KF.
* config/mips/mips.md (cpu): Add 5kf name.
(includes): Includes 5k.md.
* config/mips/5k.md: New DFA pipeline for the 5kc/5kf.
* doc/invoke.texi (MIPS Options): Updated cpu name supported with
-march flag.
From-SVN: r102560
-rw-r--r-- | gcc/ChangeLog | 11 | ||||
-rw-r--r-- | gcc/config/mips/5k.md | 230 | ||||
-rw-r--r-- | gcc/config/mips/mips.c | 22 | ||||
-rw-r--r-- | gcc/config/mips/mips.h | 1 | ||||
-rw-r--r-- | gcc/config/mips/mips.md | 3 | ||||
-rw-r--r-- | gcc/doc/invoke.texi | 12 |
6 files changed, 273 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0acf31f..f63c42e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2005-07-29 David Ung <davidu@mips.com> + + * config/mips/mips.c (mips_cpu_info_table): Add 5kf to the table. + (mips_rtx_cost_data): Add costs for 5kc and 5kf. + * config/mips/mips.h (processor_type): Add PROCESSOR_5KF. + * config/mips/mips.md (cpu): Add 5kf name. + (includes): Includes 5k.md. + * config/mips/5k.md: New DFA pipeline for the 5kc/5kf. + * doc/invoke.texi (MIPS Options): Updated cpu name supported with + -march flag. + 2005-07-29 Diego Novillo <dnovillo@redhat.com> PR 22550 diff --git a/gcc/config/mips/5k.md b/gcc/config/mips/5k.md new file mode 100644 index 0000000..0fa588a --- /dev/null +++ b/gcc/config/mips/5k.md @@ -0,0 +1,230 @@ +;; DFA-based pipeline descriptions for MIPS32 5K processor family +;; Contributed by David Ung (davidu@mips.com) +;; and Nigel Stephens (nigel@mips.com) +;; +;; References: +;; "MIPS64 5K Processor Core Family Software User's Manual, +;; Doc no: MD00012, Rev 2.09, Jan 28, 2005." +;; +;; 5Kc - Single issue with no floating point unit. +;; 5kf - Separate floating point pipe which can dual-issue with the +;; integer pipe. +;; +;; Copyright (C) 2005 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 2, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to the +;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, +;; MA 02110-1301, USA. + +(define_automaton "r5k_cpu, r5k_mdu, r5k_fpu") + +;; Integer execution unit. +(define_cpu_unit "r5k_ixu_arith" "r5k_cpu") +(define_cpu_unit "r5k_ixu_mpydiv" "r5k_mdu") +(define_cpu_unit "r5kf_fpu_arith" "r5k_fpu") + +(define_insn_reservation "r5k_int_load" 2 + (and (eq_attr "cpu" "5kc,5kf") + (eq_attr "type" "load")) + "r5k_ixu_arith") + +(define_insn_reservation "r5k_int_prefetch" 1 + (and (eq_attr "cpu" "5kc,5kf") + (eq_attr "type" "prefetch,prefetchx")) + "r5k_ixu_arith") + +(define_insn_reservation "r5k_int_store" 1 + (and (eq_attr "cpu" "5kc,5kf") + (eq_attr "type" "store")) + "r5k_ixu_arith") + +;; Divides +(define_insn_reservation "r5k_int_divsi" 34 + (and (eq_attr "cpu" "5kc,5kf") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "!DI"))) + "r5k_ixu_arith+(r5k_ixu_mpydiv*34)") + +(define_insn_reservation "r5k_int_divdi" 66 + (and (eq_attr "cpu" "5kc,5kf") + (and (eq_attr "type" "idiv") + (eq_attr "mode" "DI"))) + "r5k_ixu_arith+(r5k_ixu_mpydiv*66)") + +;; 32x32 multiply +;; 32x16 is faster, but there's no way to detect this +(define_insn_reservation "r5k_int_mult" 2 + (and (eq_attr "cpu" "5kc,5kf") + (and (eq_attr "type" "imul,imadd") + (eq_attr "mode" "SI"))) + "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") + +;; 64x64 multiply +(define_insn_reservation "r5k_int_mult_64" 9 + (and (eq_attr "cpu" "5kc,5kf") + (and (eq_attr "type" "imul,imadd") + (eq_attr "mode" "DI"))) + "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") + +;; 3 operand MUL 32x32 +(define_insn_reservation "r5k_int_mul" 4 + (and (eq_attr "cpu" "5kc,5kf") + (and (eq_attr "type" "imul3") + (eq_attr "mode" "SI"))) + "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") + +;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency. +(define_insn_reservation "r5k_int_mthilo" 1 + (and (eq_attr "cpu" "5kc,5kf") + (eq_attr "type" "mthilo")) + "r5k_ixu_arith+r5k_ixu_mpydiv") + +;; Move from HI/LO -> integer operation has a 2 cycle latency. +(define_insn_reservation "r5k_int_mfhilo" 2 + (and (eq_attr "cpu" "5kc,5kf") + (eq_attr "type" "mfhilo")) + "r5k_ixu_arith+r5k_ixu_mpydiv") + +;; All other integer insns. +(define_insn_reservation "r5k_int_alu" 1 + (and (eq_attr "cpu" "5kc,5kf") + (eq_attr "type" "arith,condmove,shift,const,nop,slt")) + "r5k_ixu_arith") + +(define_insn_reservation "r5k_int_branch" 1 + (and (eq_attr "cpu" "5kc,5kf") + (eq_attr "type" "branch")) + "r5k_ixu_arith") + +;; JR/JALR always cause one pipeline bubble because of interlock. +(define_insn_reservation "r5k_int_jump" 2 + (and (eq_attr "cpu" "5kc,5kf") + (eq_attr "type" "jump,call")) + "r5k_ixu_arith") + +;; Any -> JR/JALR (without dependency) : 1 clock issue delay +;; Any -> JR/JALR (with dependency) : 2 clock issue delay +;; load -> JR/JALR (with dependency) : 3 clock issue delay +;; mfhilo -> JR/JALR (with dependency) : 3 clock issue delay +;; mul -> JR/JALR (with dependency) : 3 clock issue delay +(define_bypass 2 "r5k_int_alu" "r5k_int_jump") +(define_bypass 3 "r5k_int_load" "r5k_int_jump") +(define_bypass 3 "r5k_int_mfhilo" "r5k_int_jump") +(define_bypass 3 "r5k_int_mul" "r5k_int_jump") + +;; Unknown or multi - single issue +(define_insn_reservation "r5k_int_unknown" 1 + (and (eq_attr "cpu" "5kc,5kf") + (eq_attr "type" "unknown,multi")) + "r5k_ixu_arith+r5k_ixu_mpydiv") + + +;; Floating Point Instructions +;; The 5Kf is a partial dual-issue cpu which can dual issue an integer +;; and floating-point instruction in the same cycle. + +;; fadd, fabs, fneg +(define_insn_reservation "r5kf_fadd" 4 + (and (eq_attr "cpu" "5kf") + (eq_attr "type" "fadd,fabs,fneg")) + "r5kf_fpu_arith") + +;; fmove, fcmove +(define_insn_reservation "r5kf_fmove" 4 + (and (eq_attr "cpu" "5kf") + (eq_attr "type" "fmove")) + "r5kf_fpu_arith") + +;; fload +(define_insn_reservation "r5kf_fload" 3 + (and (eq_attr "cpu" "5kf") + (eq_attr "type" "fpload,fpidxload")) + "r5kf_fpu_arith") + +;; fstore +(define_insn_reservation "r5kf_fstore" 1 + (and (eq_attr "cpu" "5kf") + (eq_attr "type" "fpstore")) + "r5kf_fpu_arith") + +;; fmul, fmadd +(define_insn_reservation "r5kf_fmul_sf" 4 + (and (eq_attr "cpu" "5kf") + (and (eq_attr "type" "fmul,fmadd") + (eq_attr "mode" "SF"))) + "r5kf_fpu_arith") + +(define_insn_reservation "r5kf_fmul_df" 5 + (and (eq_attr "cpu" "5kf") + (and (eq_attr "type" "fmul,fmadd") + (eq_attr "mode" "DF"))) + "r5kf_fpu_arith*2") + +;; fdiv, fsqrt, frsqrt +(define_insn_reservation "r5kf_fdiv_sf" 17 + (and (eq_attr "cpu" "5kf") + (and (eq_attr "type" "fdiv,fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "r5kf_fpu_arith*14") + +(define_insn_reservation "r5kf_fdiv_df" 32 + (and (eq_attr "cpu" "5kf") + (and (eq_attr "type" "fdiv,fsqrt") + (eq_attr "mode" "DF"))) + "r5kf_fpu_arith*29") + +;; frsqrt +(define_insn_reservation "r5kf_frsqrt_df" 35 + (and (eq_attr "cpu" "5kf") + (and (eq_attr "type" "frsqrt") + (eq_attr "mode" "DF"))) + "r5kf_fpu_arith*31") + +;; fcmp +(define_insn_reservation "r5kf_fcmp" 2 + (and (eq_attr "cpu" "5kf") + (eq_attr "type" "fcmp")) + "r5kf_fpu_arith") + +;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on condition) +(define_bypass 1 "r5kf_fcmp" "r5kf_fmove") + +;; fcvt (cvt.d.s, cvt.[sd].[wl] +(define_insn_reservation "r5kf_fcvt_d2s" 4 + (and (eq_attr "cpu" "5kf") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "I2S,I2D,S2D"))) + "r5kf_fpu_arith") + +;; fcvt (cvt.s.d) +(define_insn_reservation "r5kf_fcvt_s2d" 6 + (and (eq_attr "cpu" "5kc") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "D2S"))) + "r5kf_fpu_arith") + +;; fcvt (cvt.[wl].[sd], etc) +(define_insn_reservation "r5kf_fcvt_f2i" 5 + (and (eq_attr "cpu" "5kf") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "S2I,D2I"))) + "r5kf_fpu_arith") + +;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue +(define_insn_reservation "r5kf_fxfer" 2 + (and (eq_attr "cpu" "5kf") + (eq_attr "type" "xfer")) + "r5k_ixu_arith+r5kf_fpu_arith") diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 63eb694..ba4efb3 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -748,6 +748,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = { /* MIPS64 */ { "5kc", PROCESSOR_5KC, 64 }, + { "5kf", PROCESSOR_5KF, 64 }, { "20kc", PROCESSOR_20KC, 64 }, { "sb1", PROCESSOR_SB1, 64 }, { "sr71000", PROCESSOR_SR71000, 64 }, @@ -813,7 +814,26 @@ static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] = 4 /* memory_latency */ }, { /* 5KC */ - DEFAULT_COSTS + SOFT_FP_COSTS, + COSTS_N_INSNS (4), /* int_mult_si */ + COSTS_N_INSNS (11), /* int_mult_di */ + COSTS_N_INSNS (36), /* int_div_si */ + COSTS_N_INSNS (68), /* int_div_di */ + 1, /* branch_cost */ + 4 /* memory_latency */ + }, + { /* 5KF */ + COSTS_N_INSNS (4), /* fp_add */ + COSTS_N_INSNS (4), /* fp_mult_sf */ + COSTS_N_INSNS (5), /* fp_mult_df */ + COSTS_N_INSNS (17), /* fp_div_sf */ + COSTS_N_INSNS (32), /* fp_div_df */ + COSTS_N_INSNS (4), /* int_mult_si */ + COSTS_N_INSNS (11), /* int_mult_di */ + COSTS_N_INSNS (36), /* int_div_si */ + COSTS_N_INSNS (68), /* int_div_di */ + 1, /* branch_cost */ + 4 /* memory_latency */ }, { /* 20KC */ DEFAULT_COSTS diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index cc38e11..b68075a 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -36,6 +36,7 @@ enum processor_type { PROCESSOR_4KC, PROCESSOR_4KP, PROCESSOR_5KC, + PROCESSOR_5KF, PROCESSOR_20KC, PROCESSOR_24K, PROCESSOR_24KX, diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index a43a0c2..b0ceff8 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -336,7 +336,7 @@ ;; Attribute describing the processor. This attribute must match exactly ;; with the processor_type enumeration in mips.h. (define_attr "cpu" - "r3000,4kc,4kp,5kc,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000" + "r3000,4kc,4kp,5kc,5kf,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000" (const (symbol_ref "mips_tune"))) ;; The type of hardware hazard associated with this instruction. @@ -571,6 +571,7 @@ (define_cpu_unit "imuldiv" "imuldiv") (include "4k.md") +(include "5k.md") (include "24k.md") (include "3000.md") (include "4000.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 1605f8d..f59ef6d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -9909,13 +9909,17 @@ The ISA names are: @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4}, @samp{mips32}, @samp{mips32r2}, and @samp{mips64}. The processor names are: -@samp{4kc}, @samp{4kp}, @samp{5kc}, @samp{20kc}, +@samp{4kc}, @samp{4km}, @samp{4kp}, +@samp{5kc}, @samp{5kf}, +@samp{20kc}, +@samp{24k}, @samp{24kc}, @samp{24kf}, @samp{24kx}, @samp{m4k}, -@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400}, -@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000}, @samp{rm7000}, -@samp{rm9000}, @samp{orion}, +@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400}, +@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000}, +@samp{rm7000}, @samp{rm9000}, @samp{sb1}, +@samp{sr71000}, @samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300}, @samp{vr5000}, @samp{vr5400} and @samp{vr5500}. The special value @samp{from-abi} selects the |