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authorAndre Vieira <andre.simoesdiasvieira@arm.com>2022-03-08 17:46:40 +0000
committerAndre Vieira <andre.simoesdiasvieira@arm.com>2022-03-08 17:50:51 +0000
commit796f5220c808bc37adbd1081476589ab1a5d7ac3 (patch)
tree6aced8f7717aec1f6bc765875b7c90d201a91b38
parent6319391d5634ceb07abfadfaabee25e403f5110a (diff)
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arm: MVE: Relax addressing modes for full loads and stores
This patch relaxes the addressing modes for the mve full load and stores (by full loads and stores I mean non-widening or narrowing loads and stores resp). The code before was requiring a LO_REGNUM for these, where this is only a requirement if the load is widening or the store narrowing. gcc/ChangeLog: PR target/104790 * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO. * config/arm/arm.cc (mve_vector_mem_operand): Relax constraint on base register for non widening loads or narrowing stores.
-rw-r--r--gcc/config/arm/arm.cc25
-rw-r--r--gcc/config/arm/arm.h4
2 files changed, 17 insertions, 12 deletions
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 14b6c80..e062361 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -13521,27 +13521,28 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict)
case E_V16QImode:
case E_V8QImode:
case E_V4QImode:
- if (abs (val) <= 127)
- return (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)
- || reg_no >= FIRST_PSEUDO_REGISTER;
- return FALSE;
+ if (abs (val) > 127)
+ return FALSE;
+ break;
case E_V8HImode:
case E_V8HFmode:
case E_V4HImode:
case E_V4HFmode:
- if (val % 2 == 0 && abs (val) <= 254)
- return reg_no <= LAST_LO_REGNUM
- || reg_no >= FIRST_PSEUDO_REGISTER;
- return FALSE;
+ if (val % 2 != 0 || abs (val) > 254)
+ return FALSE;
+ break;
case E_V4SImode:
case E_V4SFmode:
- if (val % 4 == 0 && abs (val) <= 508)
- return (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)
- || reg_no >= FIRST_PSEUDO_REGISTER;
- return FALSE;
+ if (val % 4 != 0 || abs (val) > 508)
+ return FALSE;
+ break;
default:
return FALSE;
}
+ return reg_no >= FIRST_PSEUDO_REGISTER
+ || (MVE_STN_LDW_MODE (mode)
+ ? reg_no <= LAST_LO_REGNUM
+ : (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM));
}
return FALSE;
}
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index ef7b66f..f479540 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1099,6 +1099,10 @@ extern const int arm_arch_cde_coproc_bits[];
((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \
|| (MODE) == V16QImode)
+/* Modes used in MVE's narrowing stores or widening loads. */
+#define MVE_STN_LDW_MODE(MODE) \
+ ((MODE) == V4QImode || (MODE) == V8QImode || (MODE) == V4HImode)
+
#define VALID_MVE_SF_MODE(MODE) \
((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode)