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| author | H.J. Lu <hongjiu.lu@intel.com> | 2018-10-14 20:39:05 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2018-10-14 13:39:05 -0700 |
| commit | 77919e6aff5bfbe4f694dafb168b668740914b16 (patch) | |
| tree | ea5c9c13fad1b6bf2b5d5a9750f5156e13704230 | |
| parent | 190667ae2509700bc2ddda4be0934249bdd30e9c (diff) | |
| download | gcc-77919e6aff5bfbe4f694dafb168b668740914b16.zip gcc-77919e6aff5bfbe4f694dafb168b668740914b16.tar.gz gcc-77919e6aff5bfbe4f694dafb168b668740914b16.tar.bz2 | |
i386: Add register source to movddup
Add register source to movddup so that IRA will allow register source
for *vec_dupv2di when SSE3 is enabled.
gcc/
PR target/87599
* config/i386/sse.md (*vec_dupv2di): Add register source to
movddup.
gcc/testsuite/
PR target/87599
* gcc.target/i386/pr87599.c: New test.
From-SVN: r265151
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr87599.c | 12 |
4 files changed, 24 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e6c6dbc..8144181 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2018-10-14 H.J. Lu <hongjiu.lu@intel.com> + PR target/87599 + * config/i386/sse.md (*vec_dupv2di): Add register source to + movddup. + +2018-10-14 H.J. Lu <hongjiu.lu@intel.com> + PR target/87572 * common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512F_UNSET): Add OPTION_MASK_ISA_AVX512IFMA_UNSET, diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 9fc5819..ff9f815 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17864,7 +17864,7 @@ (define_insn "*vec_dupv2di" [(set (match_operand:V2DI 0 "register_operand" "=x,v,v,x") (vec_duplicate:V2DI - (match_operand:DI 1 "nonimmediate_operand" " 0,Yv,m,0")))] + (match_operand:DI 1 "nonimmediate_operand" " 0,Yv,vm,0")))] "TARGET_SSE" "@ punpcklqdq\t%0, %0 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d8fbbcc..8824474 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2018-10-14 H.J. Lu <hongjiu.lu@intel.com> + PR target/87599 + * gcc.target/i386/pr87599.c: New test. + +2018-10-14 H.J. Lu <hongjiu.lu@intel.com> + PR target/87572 * gcc.target/i386/pr87572.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/pr87599.c b/gcc/testsuite/gcc.target/i386/pr87599.c new file mode 100644 index 0000000..1e2defd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr87599.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-march=corei7 -O2" } */ +/* { dg-final { scan-assembler-times "punpcklqdq\[ \\t\]+%xmm\[0-9\]+,\[ \\t\]+%xmm\[0-9\]+" 1 } } */ + +#include <immintrin.h> + +__m128i +foo (long long val) +{ + __m128i rval = {val, val}; + return rval; +} |