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| author | Peter Bergner <bergner@vnet.ibm.com> | 2018-03-05 09:52:11 -0600 |
|---|---|---|
| committer | Peter Bergner <bergner@gcc.gnu.org> | 2018-03-05 09:52:11 -0600 |
| commit | 75a741e87be51079ae6babbd7a8828a9b57dca79 (patch) | |
| tree | f69f98f9536f2c5d3169447588ea1115e002e95b | |
| parent | 5625e74790579b589106e717dba7820933e541f1 (diff) | |
| download | gcc-75a741e87be51079ae6babbd7a8828a9b57dca79.zip gcc-75a741e87be51079ae6babbd7a8828a9b57dca79.tar.gz gcc-75a741e87be51079ae6babbd7a8828a9b57dca79.tar.bz2 | |
re PR target/84264 (ICE in rs6000_emit_le_vsx_store, at config/rs6000/rs6000.c:10367 starting with r256656)
gcc/
PR target/84264
* config/rs6000/vector.md (mov<mode>): Disallow altivec memory operands.
gcc/testsuite/
PR target/84264
* g++.dg/pr84264.C: New test.
From-SVN: r258251
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/vector.md | 11 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/g++.dg/pr84264.C | 15 |
4 files changed, 34 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c523256..723e718b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-03-05 Peter Bergner <bergner@vnet.ibm.com> + + PR target/84264 + * config/rs6000/vector.md (mov<mode>): Disallow altivec memory operands. + 2018-03-05 Richard Biener <rguenther@suse.de> PR tree-optimization/84486 diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 6e2576e..d27079b 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -132,12 +132,19 @@ && !vlogical_operand (operands[1], <MODE>mode)) operands[1] = force_reg (<MODE>mode, operands[1]); } + /* When generating load/store instructions to/from VSX registers on + pre-power9 hardware in little endian mode, we need to emit register + permute instructions to byte swap the contents, since the VSX load/store + instructions do not include a byte swap as part of their operation. + Altivec loads and stores have no such problem, so we skip them below. */ if (!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR && !gpr_or_gpr_p (operands[0], operands[1]) - && (memory_operand (operands[0], <MODE>mode) - ^ memory_operand (operands[1], <MODE>mode))) + && ((memory_operand (operands[0], <MODE>mode) + && !altivec_indexed_or_indirect_operand(operands[0], <MODE>mode)) + ^ (memory_operand (operands[1], <MODE>mode) + && !altivec_indexed_or_indirect_operand(operands[1], <MODE>mode)))) { rs6000_emit_le_vsx_move (operands[0], operands[1], <MODE>mode); DONE; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 44543c31..70bce76 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-03-05 Peter Bergner <bergner@vnet.ibm.com> + + PR target/84264 + * g++.dg/pr84264.C: New test. + 2018-03-05 Paolo Carlini <paolo.carlini@oracle.com> PR c++/84618 diff --git a/gcc/testsuite/g++.dg/pr84264.C b/gcc/testsuite/g++.dg/pr84264.C new file mode 100644 index 0000000..4f8a77d --- /dev/null +++ b/gcc/testsuite/g++.dg/pr84264.C @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-w -O1 -fstack-protector-strong" } */ + +void _setjmp (); +void a (unsigned long *); +void +b (void) +{ + for (;;) + { + _setjmp (); + unsigned long args[9]{}; + a (args); + } +} |