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authorMaciej W. Rozycki <macro@codesourcery.com>2013-07-30 18:34:43 +0000
committerMaciej W. Rozycki <macro@gcc.gnu.org>2013-07-30 18:34:43 +0000
commit72be589b8c10def0500a20ed9fe8f371317d7d70 (patch)
tree78130976047e4bd4145288cc28fb940d4140c951
parent9a92fa8b6670cf1016ca93283aa6740ef0afdfb3 (diff)
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mips16.S (DELAYf): Alias to DELAYt for the MIPS IV ISA and up.
* config/mips/mips16.S (DELAYf): Alias to DELAYt for the MIPS IV ISA and up. From-SVN: r201350
-rw-r--r--libgcc/ChangeLog5
-rw-r--r--libgcc/config/mips/mips16.S5
2 files changed, 10 insertions, 0 deletions
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 78700d7..2b5ad4d 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-07-30 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/mips/mips16.S (DELAYf): Alias to DELAYt for the MIPS IV
+ ISA and up.
+
2013-07-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/s390/linux-unwind.h: Use the proper dwarf to hard reg
diff --git a/libgcc/config/mips/mips16.S b/libgcc/config/mips/mips16.S
index 8267501..944c7c8 100644
--- a/libgcc/config/mips/mips16.S
+++ b/libgcc/config/mips/mips16.S
@@ -89,8 +89,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
OPCODE, OP2; \
.set reorder
+#if __mips >= 4
+/* Coprocessor moves are interlocked from the MIPS IV ISA up. */
+#define DELAYf(T, OPCODE, OP2) DELAYt (T, OPCODE, OP2)
+#else
/* Use "OPCODE. OP2" and jump to T. */
#define DELAYf(T, OPCODE, OP2) OPCODE, OP2; jr T
+#endif
/* MOVE_SF_BYTE0(D)
Move the first single-precision floating-point argument between