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| author | Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> | 2006-07-27 12:21:39 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@gcc.gnu.org> | 2006-07-27 12:21:39 +0000 |
| commit | 721cedf2517390c2fd7b7f2c3272177ff1a50f10 (patch) | |
| tree | d8734e1751950205738930e7cc4522590ecd1bd8 | |
| parent | 5587bfea5368088b84a7627c3c305532579fd7af (diff) | |
| download | gcc-721cedf2517390c2fd7b7f2c3272177ff1a50f10.zip gcc-721cedf2517390c2fd7b7f2c3272177ff1a50f10.tar.gz gcc-721cedf2517390c2fd7b7f2c3272177ff1a50f10.tar.bz2 | |
re PR target/28508 (Assembler Error: operand out of range (145 not between -128 and 127) form m32r-target)
PR gcc/28508
* config/m32r/m32r.md (branch_insn): Reduce pc range for short branch.
(rev_branch_insn): Likewise.
From-SVN: r115773
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/m32r/m32r.md | 14 |
2 files changed, 15 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6987f9c..31261ce 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2006-07-27 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + PR gcc/28508 + * config/m32r/m32r.md (branch_insn): Reduce pc range for short + branch. + (rev_branch_insn): Likewise. + 2006-07-27 Jan Hubicka <jh@suse.cz> PR rtl-optimization/28071 diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md index 9b35d14..552dd3f 100644 --- a/gcc/config/m32r/m32r.md +++ b/gcc/config/m32r/m32r.md @@ -1378,15 +1378,16 @@ return instruction; }" [(set_attr "type" "branch") - ; We use 400/800 instead of 512,1024 to account for inaccurate insn + ; cf PR gcc/28508 + ; We use 300/600 instead of 512,1024 to account for inaccurate insn ; lengths and insn alignments that are complex to track. ; It's not important that we be hyper-precise here. It may be more ; important blah blah blah when the chip supports parallel execution ; blah blah blah but until then blah blah blah this is simple and ; suffices. (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc)) - (const_int 400)) - (const_int 800)) + (const_int 300)) + (const_int 600)) (const_int 2) (const_int 4)))]) @@ -1407,15 +1408,16 @@ return instruction; }" [(set_attr "type" "branch") - ; We use 400/800 instead of 512,1024 to account for inaccurate insn + ; cf PR gcc/28508 + ; We use 300/600 instead of 512,1024 to account for inaccurate insn ; lengths and insn alignments that are complex to track. ; It's not important that we be hyper-precise here. It may be more ; important blah blah blah when the chip supports parallel execution ; blah blah blah but until then blah blah blah this is simple and ; suffices. (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc)) - (const_int 400)) - (const_int 800)) + (const_int 300)) + (const_int 600)) (const_int 2) (const_int 4)))]) |