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author | Pan Li <pan2.li@intel.com> | 2023-07-04 20:26:11 +0800 |
---|---|---|
committer | Pan Li <pan2.li@intel.com> | 2023-07-05 22:26:37 +0800 |
commit | 70b041684a2222b8f19200cc240a13d703b210a7 (patch) | |
tree | 116050c2a9b94e45d82c7e3ac8061578ea6fe755 | |
parent | 429905d809bbf2398bf666d65322b87ac7381e43 (diff) | |
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RISC-V: Use FRM_DYN when add the rounding mode operand
This patch would like to take FRM_DYN const rtx as the rounding mode
operand according to the RVV spec, which takes the dyn as the only
rounding mode for floating-point.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_exact_insn): Use FRM_DYN instead of const0.
Signed-off-by: Pan Li <pan2.li@intel.com>
-rw-r--r-- | gcc/config/riscv/riscv-vector-builtins.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 648c765..3a53b56 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3569,11 +3569,10 @@ function_expander::use_exact_insn (insn_code icode) if (base->has_rounding_mode_operand_p ()) add_input_operand (call_expr_nargs (exp) - 2); - /* TODO: Currently, we don't support intrinsic that is modeling rounding mode. - We add default rounding mode for the intrinsics that didn't model rounding - mode yet. */ + /* The RVV floating-point only support dynamic rounding mode in the + FRM register. */ if (opno != insn_data[icode].n_generator_args) - add_input_operand (Pmode, const0_rtx); + add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode)); return generate_insn (icode); } |