AVX10.2 ymm rounding: Support vfmulcph and vfnmadd{132,231,213}p{s,d,h} intrins

gcc/ChangeLog:

	* config/i386/avx10_2roundingintrin.h: New intrins.
	* config/i386/i386-builtin.def (BDESC): Add new builtins.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx-1.c: Add new builtin test.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Add new macro test.
	* gcc.target/i386/sse-23.c: Ditto.
	* gcc.target/i386/avx10_2-rounding-3.c: Add test.

8 files changed, 363 insertions, 0 deletions

diff --git a/gcc/config/i386/avx10_2roundingintrin.h b/gcc/config/i386/avx10_2roundingintrin.h
index 346a32c..3f833bf 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -2697,6 +2697,185 @@ _mm256_maskz_fmsubadd_round_ps (__mmask8 __U, __m256 __A, __m256 __B,
 							     (__mmask8) __U,
 							     __R);
 }
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fmul_round_pch (__m256h __B, __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmulcph256_round ((__v16hf) __B,
+						     (__v16hf) __D,
+						     __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fmul_round_pch (__m256h __A, __mmask8 __U, __m256h __B,
+			    __m256h __D, const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmulcph256_mask_round ((__v16hf) __B,
+							  (__v16hf) __D,
+							  (__v16hf) __A,
+							  (__mmask16) __U,
+							  __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fmul_round_pch (__mmask8 __U, __m256h __B, __m256h __D,
+			     const int __R)
+{
+  return (__m256h) __builtin_ia32_vfmulcph256_mask_round ((__v16hf) __B,
+							  (__v16hf) __D,
+							  (__v16hf)
+							  _mm256_setzero_ph (),
+							  (__mmask16) __U,
+							  __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fnmadd_round_pd (__m256d __A, __m256d __B, __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmaddpd256_mask_round ((__v4df) __A,
+							   (__v4df) __B,
+							   (__v4df) __D,
+							   (__mmask8) -1,
+							   __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fnmadd_round_pd (__m256d __A, __mmask8 __U, __m256d __B,
+			     __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmaddpd256_mask_round ((__v4df) __A,
+							   (__v4df) __B,
+							   (__v4df) __D,
+							   (__mmask8) __U,
+							   __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fnmadd_round_pd (__m256d __A, __m256d __B, __m256d __D,
+			      __mmask8 __U, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmaddpd256_mask3_round ((__v4df) __A,
+							    (__v4df) __B,
+							    (__v4df) __D,
+							    (__mmask8) __U,
+							    __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fnmadd_round_pd (__mmask8 __U, __m256d __A, __m256d __B,
+			      __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmaddpd256_maskz_round ((__v4df) __A,
+							    (__v4df) __B,
+							    (__v4df) __D,
+							    (__mmask8) __U,
+							    __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fnmadd_round_ph (__m256h __A, __m256h __B, __m256h __D, const int __R)
+{
+  return (__m256h)
+    __builtin_ia32_vfnmaddph256_mask_round ((__v16hf) __A,
+					    (__v16hf) __B,
+					    (__v16hf) __D,
+					    (__mmask16) -1,
+					    __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fnmadd_round_ph (__m256h __A, __mmask16 __U, __m256h __B,
+			     __m256h __D, const int __R)
+{
+  return (__m256h)
+    __builtin_ia32_vfnmaddph256_mask_round ((__v16hf) __A,
+					    (__v16hf) __B,
+					    (__v16hf) __D,
+					    (__mmask16) __U,
+					    __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fnmadd_round_ph (__m256h __A, __m256h __B, __m256h __D,
+			      __mmask16 __U, const int __R)
+{
+  return (__m256h)
+    __builtin_ia32_vfnmaddph256_mask3_round ((__v16hf) __A,
+					     (__v16hf) __B,
+					     (__v16hf) __D,
+					     (__mmask16) __U,
+					     __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fnmadd_round_ph (__mmask16 __U, __m256h __A, __m256h __B,
+			      __m256h __D, const int __R)
+{
+  return (__m256h)
+    __builtin_ia32_vfnmaddph256_maskz_round ((__v16hf) __A,
+					     (__v16hf) __B,
+					     (__v16hf) __D,
+					     (__mmask16) __U,
+					     __R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fnmadd_round_ps (__m256 __A, __m256 __B, __m256 __D, const int __R)
+{
+  return (__m256) __builtin_ia32_vfnmaddps256_mask_round ((__v8sf) __A,
+							  (__v8sf) __B,
+							  (__v8sf) __D,
+							  (__mmask8) -1,
+							  __R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fnmadd_round_ps (__m256 __A, __mmask8 __U, __m256 __B,
+			     __m256 __D, const int __R)
+{
+  return (__m256) __builtin_ia32_vfnmaddps256_mask_round ((__v8sf) __A,
+							  (__v8sf) __B,
+							  (__v8sf) __D,
+							  (__mmask8) __U,
+							  __R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fnmadd_round_ps (__m256 __A, __m256 __B, __m256 __D,
+			      __mmask8 __U, const int __R)
+{
+  return (__m256) __builtin_ia32_vfnmaddps256_mask3_round ((__v8sf) __A,
+							   (__v8sf) __B,
+							   (__v8sf) __D,
+							   (__mmask8) __U,
+							   __R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fnmadd_round_ps (__mmask8 __U, __m256 __A, __m256 __B,
+			      __m256 __D, const int __R)
+{
+  return (__m256) __builtin_ia32_vfnmaddps256_maskz_round ((__v8sf) __A,
+							   (__v8sf) __B,
+							   (__v8sf) __D,
+							   (__mmask8) __U,
+							   __R);
+}
 #else
 #define _mm256_add_round_pd(A, B, R) \
   ((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \
@@ -4093,6 +4272,62 @@ _mm256_maskz_fmsubadd_round_ps (__mmask8 __U, __m256 __A, __m256 __B,
 
 #define _mm256_maskz_fmsubadd_round_ps(U, A, B, D, R)   \
   (__m256)__builtin_ia32_vfmsubaddps256_maskz_round (A, B, D, U, R)
+
+#define _mm256_fmul_round_pch(B, D, R) \
+  ((__m256h) __builtin_ia32_vfmulcph256_round ((__v16hf) (B), \
+					       (__v16hf) (D), \
+					       (R)))
+
+#define _mm256_mask_fmul_round_pch(A, U, B, D, R) \
+  ((__m256h) __builtin_ia32_vfmulcph256_mask_round ((__v16hf) (B), \
+						    (__v16hf) (D), \
+						    (__v16hf) (A), \
+						    (__mmask16) (U), \
+						    (R)))
+
+#define _mm256_maskz_fmul_round_pch(U, B, D, R) \
+  ((__m256h) __builtin_ia32_vfmulcph256_mask_round ((__v16hf) (B), \
+						    (__v16hf) (D), \
+						    (__v16hf) \
+						    (_mm256_setzero_ph ()), \
+						    (__mmask16) (U), \
+						    (R)))
+
+#define _mm256_fnmadd_round_pd(A, B, D, R)	      \
+  (__m256d)__builtin_ia32_vfnmaddpd256_mask_round (A, B, D, -1, R)
+
+#define _mm256_mask_fnmadd_round_pd(A, U, B, D, R)    \
+  (__m256d)__builtin_ia32_vfnmaddpd256_mask_round (A, B, D, U, R)
+
+#define _mm256_mask3_fnmadd_round_pd(A, B, D, U, R)   \
+  (__m256d)__builtin_ia32_vfnmaddpd256_mask3_round (A, B, D, U, R)
+
+#define _mm256_maskz_fnmadd_round_pd(U, A, B, D, R)   \
+  (__m256d)__builtin_ia32_vfnmaddpd256_maskz_round (A, B, D, U, R)
+
+#define _mm256_fnmadd_round_ph(A, B, D, R)	    \
+  ((__m256h)__builtin_ia32_vfnmaddph256_mask_round ((A), (B), (D), -1, (R)))
+
+#define _mm256_mask_fnmadd_round_ph(A, U, B, D, R)	  \
+  ((__m256h)__builtin_ia32_vfnmaddph256_mask_round ((A), (B), (D), (U), (R)))
+
+#define _mm256_mask3_fnmadd_round_ph(A, B, D, U, R)	  \
+  ((__m256h)__builtin_ia32_vfnmaddph256_mask3_round ((A), (B), (D), (U), (R)))
+
+#define _mm256_maskz_fnmadd_round_ph(U, A, B, D, R)	  \
+  ((__m256h)__builtin_ia32_vfnmaddph256_maskz_round ((A), (B), (D), (U), (R)))
+
+#define _mm256_fnmadd_round_ps(A, B, D, R)	      \
+  (__m256)__builtin_ia32_vfnmaddps256_mask_round (A, B, D, -1, R)
+
+#define _mm256_mask_fnmadd_round_ps(A, U, B, D, R)    \
+  (__m256)__builtin_ia32_vfnmaddps256_mask_round (A, B, D, U, R)
+
+#define _mm256_mask3_fnmadd_round_ps(A, B, D, U, R)   \
+  (__m256)__builtin_ia32_vfnmaddps256_mask3_round (A, B, D, U, R)
+
+#define _mm256_maskz_fnmadd_round_ps(U, A, B, D, R)   \
+  (__m256)__builtin_ia32_vfnmaddps256_maskz_round (A, B, D, U, R)
 #endif
 
 #define _mm256_cmul_round_pch(A, B, R) _mm256_fcmul_round_pch ((A), (B), (R))
@@ -4101,6 +4336,12 @@ _mm256_maskz_fmsubadd_round_ps (__mmask8 __U, __m256 __A, __m256 __B,
 #define _mm256_maskz_cmul_round_pch(U, A, B, R)			      \
   _mm256_maskz_fcmul_round_pch ((U), (A), (B), (R))
 
+#define _mm256_mul_round_pch(A, B, R) _mm256_fmul_round_pch ((A), (B), (R))
+#define _mm256_mask_mul_round_pch(W, U, A, B, R)		      \
+  _mm256_mask_fmul_round_pch ((W), (U), (A), (B), (R))
+#define _mm256_maskz_mul_round_pch(U, A, B, R)			      \
+  _mm256_maskz_fmul_round_pch ((U), (A), (B), (R))
+
 #ifdef __DISABLE_AVX10_2_256__
 #undef __DISABLE_AVX10_2_256__
 #pragma GCC pop_options
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index b43dfe5..98a725b 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3425,6 +3425,17 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmsubadd_v16hf_maskz_r
 BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmsubadd_v8sf_mask_round, "__builtin_ia32_vfmsubaddps256_mask_round", IX86_BUILTIN_VFMSUBADDPS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
 BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3_round, "__builtin_ia32_vfmsubaddps256_mask3_round", IX86_BUILTIN_VFMSUBADDPS512_MASK3_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
 BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmsubadd_v8sf_maskz_round, "__builtin_ia32_vfmsubaddps256_maskz_round", IX86_BUILTIN_VFMSUBADDPS256_MASKZ_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmulc_v16hf_round, "__builtin_ia32_vfmulcph256_round", IX86_BUILTIN_VFMULCPH256_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fmulc_v16hf_mask_round, "__builtin_ia32_vfmulcph256_mask_round", IX86_BUILTIN_VFMULCPH256_MASK_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v4df_mask_round, "__builtin_ia32_vfnmaddpd256_mask_round", IX86_BUILTIN_VFNMADDPD256_MASK_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v4df_mask3_round, "__builtin_ia32_vfnmaddpd256_mask3_round", IX86_BUILTIN_VFNMADDPD256_MASK3_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v4df_maskz_round, "__builtin_ia32_vfnmaddpd256_maskz_round", IX86_BUILTIN_VFNMADDPD256_MASKZ_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v16hf_mask_round, "__builtin_ia32_vfnmaddph256_mask_round", IX86_BUILTIN_VFNMADDPH256_MASK_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v16hf_mask3_round, "__builtin_ia32_vfnmaddph256_mask3_round", IX86_BUILTIN_VFNMADDPH256_MASK3_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v16hf_maskz_round, "__builtin_ia32_vfnmaddph256_maskz_round", IX86_BUILTIN_VFNMADDPH256_MASKZ_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v8sf_mask_round, "__builtin_ia32_vfnmaddps256_mask_round", IX86_BUILTIN_VFNMADDPS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v8sf_mask3_round, "__builtin_ia32_vfnmaddps256_mask3_round", IX86_BUILTIN_VFNMADDPS512_MASK3_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v8sf_maskz_round, "__builtin_ia32_vfnmaddps256_maskz_round", IX86_BUILTIN_VFNMADDPS256_MASKZ_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
 
 BDESC_END (ROUND_ARGS, MULTI_ARG)
 
diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c
index ee0ce09..7f42ee2 100644
--- a/gcc/testsuite/gcc.target/i386/avx-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx-1.c
@@ -949,6 +949,17 @@
 #define __builtin_ia32_vfmsubaddps256_mask_round(A, B, C, D, E) __builtin_ia32_vfmsubaddps256_mask_round(A, B, C, D, 8)
 #define __builtin_ia32_vfmsubaddps256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmsubaddps256_mask3_round(A, B, C, D, 8)
 #define __builtin_ia32_vfmsubaddps256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmsubaddps256_maskz_round(A, B, C, D, 8)
+#define __builtin_ia32_vfmulcph256_round(A, B, C) __builtin_ia32_vfmulcph256_round(A, B, 8)
+#define __builtin_ia32_vfmulcph256_mask_round(A, B, C, D, E) __builtin_ia32_vfmulcph256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd256_mask_round(A, B, C, D, E) __builtin_ia32_vfnmaddpd256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd256_mask3_round(A, B, C, D, E) __builtin_ia32_vfnmaddpd256_mask3_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd256_maskz_round(A, B, C, D, E) __builtin_ia32_vfnmaddpd256_maskz_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddph256_mask_round(A, B, C, D, E) __builtin_ia32_vfnmaddph256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddph256_mask3_round(A, B, C, D, E) __builtin_ia32_vfnmaddph256_mask3_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddph256_maskz_round(A, B, C, D, E) __builtin_ia32_vfnmaddph256_maskz_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps256_mask_round(A, B, C, D, E) __builtin_ia32_vfnmaddps256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps256_mask3_round(A, B, C, D, E) __builtin_ia32_vfnmaddps256_mask3_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps256_maskz_round(A, B, C, D, E) __builtin_ia32_vfnmaddps256_maskz_round(A, B, C, D, 8)
 
 #include <wmmintrin.h>
 #include <immintrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c
index 51dda96..90c4cca 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-rounding-3.c
@@ -78,6 +78,21 @@
 /* { dg-final { scan-assembler-times "vfmsubadd...ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1  }  } */
 /* { dg-final { scan-assembler-times "vfmsubadd231ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1  }  } */
 /* { dg-final { scan-assembler-times "vfmsubadd...ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 2  }  } */
+/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2  }  } */
+/* { dg-final { scan-assembler-times "vfmulcph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd231pd\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd231ph\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd231ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1  }  } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1  }  } */
 
 #include <immintrin.h>
 
@@ -241,3 +256,38 @@ avx10_2_test_11 (void)
   x = _mm256_mask3_fmsubadd_round_ps (x, x, x, m8, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
   x = _mm256_maskz_fmsubadd_round_ps (m8, x, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
 }
+
+void extern
+avx10_2_test_12 (void)
+{
+  xh = _mm256_fmul_round_pch (xh, xh, 8);
+  xh = _mm256_mask_fmul_round_pch (xh, m8, xh, xh, 8);
+  xh = _mm256_maskz_fmul_round_pch (m8, xh, xh, 11);
+}
+
+void extern
+avx10_2_test_13 (void)
+{
+  xh = _mm256_mul_round_pch (xh, xh, 8);
+  xh = _mm256_mask_mul_round_pch (xh, m8, xh, xh, 8);
+  xh = _mm256_maskz_mul_round_pch (m8, xh, xh, 11);
+}
+
+void extern
+avx10_2_test_14 (void)
+{
+  xd = _mm256_fnmadd_round_pd (xd, xd, xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  xd = _mm256_mask_fnmadd_round_pd (xd, m8, xd, xd, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  xd = _mm256_mask3_fnmadd_round_pd (xd, xd, xd, m8, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  xd = _mm256_maskz_fnmadd_round_pd (m8, xd, xd, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+
+  xh = _mm256_fnmadd_round_ph (xh, xh, xh, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  xh = _mm256_mask_fnmadd_round_ph (xh, m8, xh, xh, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  xh = _mm256_mask3_fnmadd_round_ph (xh, xh, xh, m8, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  xh = _mm256_maskz_fnmadd_round_ph (m8, xh, xh, xh, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+
+  x = _mm256_fnmadd_round_ps (x, x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm256_mask_fnmadd_round_ps (x, m8, x, x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x = _mm256_mask3_fnmadd_round_ps (x, x, x, m8, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x = _mm256_maskz_fnmadd_round_ps (m8, x, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index 4c7aea2..b6023d9 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -956,5 +956,16 @@
 #define __builtin_ia32_vfmsubaddps256_mask_round(A, B, C, D, E) __builtin_ia32_vfmsubaddps256_mask_round(A, B, C, D, 8)
 #define __builtin_ia32_vfmsubaddps256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmsubaddps256_mask3_round(A, B, C, D, 8)
 #define __builtin_ia32_vfmsubaddps256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmsubaddps256_maskz_round(A, B, C, D, 8)
+#define __builtin_ia32_vfmulcph256_round(A, B, C) __builtin_ia32_vfmulcph256_round(A, B, 8)
+#define __builtin_ia32_vfmulcph256_mask_round(A, B, C, D, E) __builtin_ia32_vfmulcph256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd256_mask_round(A, B, C, D, E) __builtin_ia32_vfnmaddpd256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd256_mask3_round(A, B, C, D, E) __builtin_ia32_vfnmaddpd256_mask3_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd256_maskz_round(A, B, C, D, E) __builtin_ia32_vfnmaddpd256_maskz_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddph256_mask_round(A, B, C, D, E) __builtin_ia32_vfnmaddph256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddph256_mask3_round(A, B, C, D, E) __builtin_ia32_vfnmaddph256_mask3_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddph256_maskz_round(A, B, C, D, E) __builtin_ia32_vfnmaddph256_maskz_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps256_mask_round(A, B, C, D, E) __builtin_ia32_vfnmaddps256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps256_mask3_round(A, B, C, D, E) __builtin_ia32_vfnmaddps256_mask3_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps256_maskz_round(A, B, C, D, E) __builtin_ia32_vfnmaddps256_maskz_round(A, B, C, D, 8)
 
 #include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
index 2e612ad..946c074 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1191,6 +1191,10 @@ test_3 (_mm256_fmsub_round_ps, __m256, __m256, __m256, __m256, 9)
 test_3 (_mm256_fmsubadd_round_pd, __m256d, __m256d, __m256d, __m256d, 9)
 test_3 (_mm256_fmsubadd_round_ph, __m256h, __m256h, __m256h, __m256h, 9)
 test_3 (_mm256_fmsubadd_round_ps, __m256, __m256, __m256, __m256, 9)
+test_3 (_mm256_maskz_fmul_round_pch, __m256h, __mmask8, __m256h, __m256h, 8)
+test_3 (_mm256_fnmadd_round_pd, __m256d, __m256d, __m256d, __m256d, 9)
+test_3 (_mm256_fnmadd_round_ph, __m256h, __m256h, __m256h, __m256h, 9)
+test_3 (_mm256_fnmadd_round_ps, __m256, __m256, __m256, __m256, 9)
 test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
 test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
 test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)
@@ -1245,6 +1249,16 @@ test_4 (_mm256_maskz_fmsubadd_round_ph, __m256h,__mmask16, __m256h, __m256h, __m
 test_4 (_mm256_mask_fmsubadd_round_ps, __m256, __m256, __mmask8, __m256, __m256, 9)
 test_4 (_mm256_mask3_fmsubadd_round_ps, __m256, __m256, __m256, __m256, __mmask8, 9)
 test_4 (_mm256_maskz_fmsubadd_round_ps, __m256,__mmask8, __m256, __m256, __m256, 9)
+test_4 (_mm256_mask_fmul_round_pch, __m256h, __m256h, __mmask8, __m256h, __m256h, 8)
+test_4 (_mm256_mask_fnmadd_round_pd, __m256d, __m256d, __mmask8, __m256d, __m256d, 9)
+test_4 (_mm256_mask3_fnmadd_round_pd, __m256d, __m256d, __m256d, __m256d, __mmask8, 9)
+test_4 (_mm256_maskz_fnmadd_round_pd, __m256d,__mmask8, __m256d, __m256d, __m256d, 9)
+test_4 (_mm256_mask_fnmadd_round_ph, __m256h, __m256h, __mmask16, __m256h, __m256h, 9)
+test_4 (_mm256_mask3_fnmadd_round_ph, __m256h, __m256h, __m256h, __m256h, __mmask16, 9)
+test_4 (_mm256_maskz_fnmadd_round_ph, __m256h,__mmask16, __m256h, __m256h, __m256h, 9)
+test_4 (_mm256_mask_fnmadd_round_ps, __m256, __m256, __mmask8, __m256, __m256, 9)
+test_4 (_mm256_mask3_fnmadd_round_ps, __m256, __m256, __m256, __m256, __mmask8, 9)
+test_4 (_mm256_maskz_fnmadd_round_ps, __m256,__mmask8, __m256, __m256, __m256, 9)
 test_4x (_mm256_maskz_fixupimm_round_pd, __m256d, __mmask8, __m256d, __m256d, __m256i, 3, 8)
 test_4x (_mm256_maskz_fixupimm_round_ps, __m256, __mmask8, __m256, __m256, __m256i, 3, 8)
 test_4x (_mm256_mask_fixupimm_round_pd, __m256d, __m256d, __mmask8, __m256d, __m256i, 3, 8)
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
index d1dbd81..1f07852 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -1233,6 +1233,10 @@ test_3 (_mm256_fmsub_round_ps, __m256, __m256, __m256, __m256, 9)
 test_3 (_mm256_fmsubadd_round_pd, __m256d, __m256d, __m256d, __m256d, 9)
 test_3 (_mm256_fmsubadd_round_ph, __m256h, __m256h, __m256h, __m256h, 9)
 test_3 (_mm256_fmsubadd_round_ps, __m256, __m256, __m256, __m256, 9)
+test_3 (_mm256_maskz_fmul_round_pch, __m256h, __mmask8, __m256h, __m256h, 8)
+test_3 (_mm256_fnmadd_round_pd, __m256d, __m256d, __m256d, __m256d, 9)
+test_3 (_mm256_fnmadd_round_ph, __m256h, __m256h, __m256h, __m256h, 9)
+test_3 (_mm256_fnmadd_round_ps, __m256, __m256, __m256, __m256, 9)
 test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
 test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
 test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)
@@ -1287,6 +1291,16 @@ test_4 (_mm256_maskz_fmsubadd_round_ph, __m256h,__mmask16, __m256h, __m256h, __m
 test_4 (_mm256_mask_fmsubadd_round_ps, __m256, __m256, __mmask8, __m256, __m256, 9)
 test_4 (_mm256_mask3_fmsubadd_round_ps, __m256, __m256, __m256, __m256, __mmask8, 9)
 test_4 (_mm256_maskz_fmsubadd_round_ps, __m256,__mmask8, __m256, __m256, __m256, 9)
+test_4 (_mm256_mask_fmul_round_pch, __m256h, __m256h, __mmask8, __m256h, __m256h, 8)
+test_4 (_mm256_mask_fnmadd_round_pd, __m256d, __m256d, __mmask8, __m256d, __m256d, 9)
+test_4 (_mm256_mask3_fnmadd_round_pd, __m256d, __m256d, __m256d, __m256d, __mmask8, 9)
+test_4 (_mm256_maskz_fnmadd_round_pd, __m256d,__mmask8, __m256d, __m256d, __m256d, 9)
+test_4 (_mm256_mask_fnmadd_round_ph, __m256h, __m256h, __mmask16, __m256h, __m256h, 9)
+test_4 (_mm256_mask3_fnmadd_round_ph, __m256h, __m256h, __m256h, __m256h, __mmask16, 9)
+test_4 (_mm256_maskz_fnmadd_round_ph, __m256h,__mmask16, __m256h, __m256h, __m256h, 9)
+test_4 (_mm256_mask_fnmadd_round_ps, __m256, __m256, __mmask8, __m256, __m256, 9)
+test_4 (_mm256_mask3_fnmadd_round_ps, __m256, __m256, __m256, __m256, __mmask8, 9)
+test_4 (_mm256_maskz_fnmadd_round_ps, __m256,__mmask8, __m256, __m256, __m256, 9)
 test_4x (_mm256_maskz_fixupimm_round_pd, __m256d, __mmask8, __m256d, __m256d, __m256i, 3, 8)
 test_4x (_mm256_maskz_fixupimm_round_ps, __m256, __mmask8, __m256, __m256, __m256i, 3, 8)
 test_4x (_mm256_mask_fixupimm_round_pd, __m256d, __m256d, __mmask8, __m256d, __m256i, 3, 8)
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index 9dc5248..125ec72 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -931,6 +931,17 @@
 #define __builtin_ia32_vfmsubaddps256_mask_round(A, B, C, D, E) __builtin_ia32_vfmsubaddps256_mask_round(A, B, C, D, 8)
 #define __builtin_ia32_vfmsubaddps256_mask3_round(A, B, C, D, E) __builtin_ia32_vfmsubaddps256_mask3_round(A, B, C, D, 8)
 #define __builtin_ia32_vfmsubaddps256_maskz_round(A, B, C, D, E) __builtin_ia32_vfmsubaddps256_maskz_round(A, B, C, D, 8)
+#define __builtin_ia32_vfmulcph256_round(A, B, C) __builtin_ia32_vfmulcph256_round(A, B, 8)
+#define __builtin_ia32_vfmulcph256_mask_round(A, B, C, D, E) __builtin_ia32_vfmulcph256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd256_mask_round(A, B, C, D, E) __builtin_ia32_vfnmaddpd256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd256_mask3_round(A, B, C, D, E) __builtin_ia32_vfnmaddpd256_mask3_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd256_maskz_round(A, B, C, D, E) __builtin_ia32_vfnmaddpd256_maskz_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddph256_mask_round(A, B, C, D, E) __builtin_ia32_vfnmaddph256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddph256_mask3_round(A, B, C, D, E) __builtin_ia32_vfnmaddph256_mask3_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddph256_maskz_round(A, B, C, D, E) __builtin_ia32_vfnmaddph256_maskz_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps256_mask_round(A, B, C, D, E) __builtin_ia32_vfnmaddps256_mask_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps256_mask3_round(A, B, C, D, E) __builtin_ia32_vfnmaddps256_mask3_round(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps256_maskz_round(A, B, C, D, E) __builtin_ia32_vfnmaddps256_maskz_round(A, B, C, D, 8)
 
 #pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512")