i386: Fix gcc.target/i386/pr101716.c (and some related cleanups)

Fix pr101716.c testcase scan-assembler failure.  The combine pass will not
combine instructions that use registers in TARGET_CLASS_LIKELY_SPILLED
class, such as %eax return register in AREG class.

Change the testcase to use pseudos only and explicitly scan for
zero_extendsidi pattern name.

While looking there, also clean ix86_decompose_address a bit: eliminate
common code and use UINTVAL and HOST_WIDE_INT_UC macros in the condition
for AND wrapped address.

gcc/ChangeLog:

	* config/i386/i386.cc (ix86_decompose_address): Eliminate
	common code and use use UINTVAL and HOST_WIDE_INT_UC macros
	in the condition for AND wrapped address.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr101716.c (dg-options): Add -dp.
	(dg-final): Scan for zero_extendsidi.
	(sample1): Change the code to use pseudos only.

2 files changed, 21 insertions, 32 deletions

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index b426d29..0cdc283 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -10806,36 +10806,26 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
 	  if (CONST_INT_P (addr))
 	    return false;
 	}
-      else if (GET_CODE (addr) == AND
-	       && const_32bit_mask (XEXP (addr, 1), DImode))
-	{
-	  addr = lowpart_subreg (SImode, XEXP (addr, 0), DImode);
-	  if (addr == NULL_RTX)
-	    return false;
-
-	  if (CONST_INT_P (addr))
-	    return false;
-	}
       else if (GET_CODE (addr) == AND)
 	{
-	  /* For ASHIFT inside AND, combine will not generate
-	     canonical zero-extend. Merge mask for AND and shift_count
-	     to check if it is canonical zero-extend.  */
-	  tmp = XEXP (addr, 0);
 	  rtx mask = XEXP (addr, 1);
-	  if (tmp && GET_CODE(tmp) == ASHIFT)
+	  rtx shift_val;
+
+	  if (const_32bit_mask (mask, DImode)
+	      /* For ASHIFT inside AND, combine will not generate
+		 canonical zero-extend. Merge mask for AND and shift_count
+		 to check if it is canonical zero-extend.  */
+	      || (CONST_INT_P (mask)
+		  && GET_CODE (XEXP (addr, 0)) == ASHIFT
+		  && CONST_INT_P (shift_val = XEXP (XEXP (addr, 0), 1))
+		  && ((UINTVAL (mask)
+		       | ((HOST_WIDE_INT_1U << INTVAL (shift_val)) - 1))
+		      == HOST_WIDE_INT_UC (0xffffffff))))
 	    {
-	      rtx shift_val = XEXP (tmp, 1);
-	      if (CONST_INT_P (mask) && CONST_INT_P (shift_val)
-		  && (((unsigned HOST_WIDE_INT) INTVAL(mask)
-		      | ((HOST_WIDE_INT_1U << INTVAL(shift_val)) - 1))
-		      == 0xffffffff))
-		{
-		  addr = lowpart_subreg (SImode, XEXP (addr, 0),
-					 DImode);
-		}
+	      addr = lowpart_subreg (SImode, XEXP (addr, 0), DImode);
+	      if (addr == NULL_RTX)
+		return false;
 	    }
-
 	}
     }
 
diff --git a/gcc/testsuite/gcc.target/i386/pr101716.c b/gcc/testsuite/gcc.target/i386/pr101716.c
index 5e3ea64..25d3c41 100644
--- a/gcc/testsuite/gcc.target/i386/pr101716.c
+++ b/gcc/testsuite/gcc.target/i386/pr101716.c
@@ -1,11 +1,10 @@
 /* PR target/101716 */
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -dp" } */
+/* { dg-final { scan-assembler-not "zero_extendsidi" } } */
 
-/* { dg-final { scan-assembler "leal\[\\t \]\[^\\n\]*eax" } } */
-/* { dg-final { scan-assembler-not "movl\[\\t \]\[^\\n\]*eax" } } */
-
-unsigned long long sample1(unsigned long long m) {
-    unsigned int t = -1;
-    return (m << 1) & t;
+void sample1 (unsigned long long x, unsigned long long *r)
+{
+  unsigned int t = -1;
+  *r = (x << 1) & t;
 }