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| author | Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> | 2024-05-02 08:43:50 +0200 |
|---|---|---|
| committer | Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> | 2024-05-02 08:43:50 +0200 |
| commit | 66f49ccd409c7a3f6eb89dd78e275ab57c983c79 (patch) | |
| tree | 3036a629b87757fbb88b3396e7bd82b455ac8706 | |
| parent | 02917ac4528e32d1b2d0da5f45ef5937c56942cd (diff) | |
| download | gcc-66f49ccd409c7a3f6eb89dd78e275ab57c983c79.zip gcc-66f49ccd409c7a3f6eb89dd78e275ab57c983c79.tar.gz gcc-66f49ccd409c7a3f6eb89dd78e275ab57c983c79.tar.bz2 | |
s390: testsuite: Fix risbg-ll-2.c
Starting with r14-2047-gd0e891406b16dc we see through subregs which
means for f10 in risbg-ll-2.c we do not end up with rosbg_si_noshift but
rather rosbg_di_noshift which materializes in slightly different start
index. This saves us an extend.
gcc/testsuite/ChangeLog:
* gcc.target/s390/risbg-ll-2.c: Fix start offset for rosbg of
f10.
| -rw-r--r-- | gcc/testsuite/gcc.target/s390/risbg-ll-2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c index 8bf1a0f..ca80602 100644 --- a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c +++ b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c @@ -113,7 +113,7 @@ i32 f9 (i64 v_x, i32 v_y) // ands with incompatible masks. i32 f10 (i64 v_x, i32 v_y) { - /* { dg-final { scan-assembler "f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,32,39,0" { target { lp64 } } } } */ + /* { dg-final { scan-assembler "f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,0,39,0" { target { lp64 } } } } */ /* { dg-final { scan-assembler "f10:\n\tnilf\t%r4,4278190080\n\trosbg\t%r4,%r2,48,63,48" { target { ! lp64 } } } } */ i64 v_shr6 = ((ui64)v_x) >> 48; i32 v_conv = (ui32)v_shr6; |