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| author | Jonathan Wright <jonathan.wright@arm.com> | 2021-08-18 09:10:22 +0100 |
|---|---|---|
| committer | Jonathan Wright <jonathan.wright@arm.com> | 2021-08-18 16:07:38 +0100 |
| commit | 640df4ef815aa35fedf1d724ab31d8eed8817f82 (patch) | |
| tree | 3ff06eb61eab0911628fb5d70e66b5288fe492c2 | |
| parent | 4fb471afc4f13ead1978fcdb008b92192412e9ba (diff) | |
| download | gcc-640df4ef815aa35fedf1d724ab31d8eed8817f82.zip gcc-640df4ef815aa35fedf1d724ab31d8eed8817f82.tar.gz gcc-640df4ef815aa35fedf1d724ab31d8eed8817f82.tar.bz2 | |
aarch64: Fix float <-> int errors in vld4[q]_lane intrinsics
A previous commit "aarch64: Remove macros for vld4[q]_lane Neon
intrinsics" introduced some float <-> int type conversion errors.
This patch fixes those errors.
gcc/ChangeLog:
2021-08-18 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/arm_neon.h (vld3_lane_f64): Use float RTL
pattern and type cast.
(vld4_lane_f32): Use float RTL pattern.
(vld4q_lane_f64): Use float type cast.
| -rw-r--r-- | gcc/config/aarch64/arm_neon.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index d8b2970..635a223 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -20546,8 +20546,8 @@ vld3_lane_f64 (const float64_t * __ptr, float64x1x3_t __b, const int __c) __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) __temp.val[0], 0); __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) __temp.val[1], 1); __o = __builtin_aarch64_set_qregciv2df (__o, (float64x2_t) __temp.val[2], 2); - __o = __builtin_aarch64_ld3_lanedi ( - (__builtin_aarch64_simd_di *) __ptr, __o, __c); + __o = __builtin_aarch64_ld3_lanedf ( + (__builtin_aarch64_simd_df *) __ptr, __o, __c); __b.val[0] = (float64x1_t) __builtin_aarch64_get_dregcidi (__o, 0); __b.val[1] = (float64x1_t) __builtin_aarch64_get_dregcidi (__o, 1); __b.val[2] = (float64x1_t) __builtin_aarch64_get_dregcidi (__o, 2); @@ -21077,7 +21077,7 @@ vld4_lane_f32 (const float32_t * __ptr, float32x2x4_t __b, const int __c) __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) __temp.val[1], 1); __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) __temp.val[2], 2); __o = __builtin_aarch64_set_qregxiv4sf (__o, (float32x4_t) __temp.val[3], 3); - __o = __builtin_aarch64_ld4_lanev2si ( + __o = __builtin_aarch64_ld4_lanev2sf ( (__builtin_aarch64_simd_sf *) __ptr, __o, __c); __b.val[0] = (float32x2_t) __builtin_aarch64_get_dregxidi (__o, 0); __b.val[1] = (float32x2_t) __builtin_aarch64_get_dregxidi (__o, 1); @@ -21381,7 +21381,7 @@ vld4q_lane_f64 (const float64_t * __ptr, float64x2x4_t __b, const int __c) __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[2], 2); __o = __builtin_aarch64_set_qregxiv4si (__o, (int32x4_t) __b.val[3], 3); __o = __builtin_aarch64_ld4_lanev2df ( - (__builtin_aarch64_simd_di *) __ptr, __o, __c); + (__builtin_aarch64_simd_df *) __ptr, __o, __c); ret.val[0] = (float64x2_t) __builtin_aarch64_get_qregxiv4si (__o, 0); ret.val[1] = (float64x2_t) __builtin_aarch64_get_qregxiv4si (__o, 1); ret.val[2] = (float64x2_t) __builtin_aarch64_get_qregxiv4si (__o, 2); |