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| author | Die Li <lidie@eswincomputing.com> | 2023-07-14 02:02:05 +0000 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-07-14 14:30:17 +0800 |
| commit | 601a412ef0fe59ce48fb8635ebdaa58b58512a5a (patch) | |
| tree | d067c42729d2b5c1d2be3dd9689616b90d22b9bb | |
| parent | 4dbb3af1efe55174a714d15c2994cf2842ef8c28 (diff) | |
| download | gcc-601a412ef0fe59ce48fb8635ebdaa58b58512a5a.zip gcc-601a412ef0fe59ce48fb8635ebdaa58b58512a5a.tar.gz gcc-601a412ef0fe59ce48fb8635ebdaa58b58512a5a.tar.bz2 | |
RISC-V: Remove the redundant expressions in the and<mode>3.
When generating the gen_and<mode>3 function based on the and<mode>3
template, it produces the expression emit_insn (gen_rtx_SET (operand0,
gen_rtx_AND (<mode>, operand1, operand2)));, which is identical to the
portion I removed in this patch. Therefore, the redundant portion can be
deleted.
Signed-off-by: Die Li <lidie@eswincomputing.com>
gcc/ChangeLog:
* config/riscv/riscv.md: Remove redundant portion in and<mode>3.
| -rw-r--r-- | gcc/config/riscv/riscv.md | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 7988026..c4f8eb9 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1491,11 +1491,6 @@ DONE; } } - else - { - emit_move_insn (operands[0], gen_rtx_AND (<MODE>mode, operands[1], operands[2])); - DONE; - } }) (define_insn "*and<mode>3" |